Signal Integrity Methodology for Double-Digit Multi-Gigabit Interfaces

October 19, 2018 Cadence PCB Solutions

As data rates for serial link interfaces such as PCI Express® (PCIe®) Gen 4 move into the double digits, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream as possible, to enable trade-offs, feasibility studies, component selection, and constraint capture.

Accurate modeling of SerDes transmitter and receiver equalization in the link are paramount to obtaining realistic simulation results, including the complex adaptive equalization that is present in nearly all high data rate serial links. Interconnect modeling also faces new challenges, with via arrays requiring full wave 3D solutions in order to accurately characterize their complex via stub and coupling behavior, threatening to drive extraction times from minutes to hours or days. After simulation, interface-specific postprocessing is often required to check transmitter, channel, and receiver compliance criteria.

This paper will suggest methodologies for creating a “virtual prototype” of your serial link pre-design, and how to create the associated interconnect and SerDes models that go with it. We will review how to utilize IBIS-AMI models, and how to build your own if they are not available when you need them. It will also show you the latest interconnect extraction techniques to give you “full wave accuracy where you need it” while keeping computational times in control, and how to use standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.

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