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Effect of Power Noise on Multi-Gigabit Serial Links

Published Date
Author Cadence PCB Solutions

This paper presents a proof-of-concept analysis that was performed to test the hypothesis that a typical printed circuit board (PCB) and package power distribution system (PDS)

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This paper presents a proof-of-concept analysis that was performed to test the hypothesis that a typical printed circuit board (PCB) and package power distribution system (PDS) has a significant impact on the signal quality of a 10Gbps serial link. In addition to the presence of the non-ideal PDS, a noise source was also set up to inject noise current into the PDS, and its result on the serial link signal quality was analyzed. The following sections are included:

  • Technical approach
  • Test vehicle description
  • Results
  • Conclusions
  • Appendix