08 - PSpice Digital Models for Circuit Simulation

Analysis types

PSpice A/D supports analyses that can simulate analog-only, mixed-signal, and digital-only circuits.

PSpice A/D fully supports digital analysis by simulating the timing behavior of digital devices within a standard transient analysis, including worst-case (min/max) timing. For mixed analog/digital circuits, all of the above-mentioned analyses can be run. If the circuit is digital-only, only the transient analysis can be run.

Table 8-1 provides a summary of the available PSpice A/D analyses and the corresponding Analysis type options where the analysis parameters are specified. In design entry tool, switch to the PSpice A/D view, then from the PSpice menu, choose New Simulation Profile.

The waveform analyzer calculates and displays the results of PSpice simulations for swept analyses. The waveform analyzer also generates supplementary analysis information in the form of lists and tables, and saves this in the simulation output file.

Setting up analyses

Specific information for setting up each type of analysis is discussed in the following chapters.

To set up one or more analyses

1. From the PSpice menu, choose New Simulation Profile.
2. Enter the name of the profile and click Create.
   The Simulation Settings dialog box appears.
3. Click the Analysis tab if it is not already the active tab in the dialog box.
4. Enter the necessary parameter values and select the appropriate check boxes to complete the analysis specifications.
   See Output variables for a description of the output variables that can be entered in the Simulation Settings dialog box displayed for an analysis type.
5. Set up any other analyses you want to perform for the circuit by selecting any of the remaining analysis types and options, then complete their setup dialog boxes.
   Specific information for setting up each type of analysis is discussed in the following chapters.

Order for standard analyses

For normal simulations that are run from a simulation profile, or in batch mode, only the particular analysis type that is specified will be run.

During simulation of a circuit file, the analysis types are performed in the order shown in Table 8-2. Each type of analysis is conducted only once per run.

Several of the analyses (small-signal transfer, DC sensitivity, and frequency response) depend upon the bias point calculation. Because so many analyses use the bias point, PSpice A/D calculates this automatically. PSpice A/D’s bias point calculation computes initial states of digital components as well as the analog components.

Output variables

Certain analyses (such as noise, Monte Carlo, sensitivity/worst-case, DC sensitivity, Fourier, and small-signal DC transfer function) require you to specify output variables for voltages and currents at specific points on the schematic. Depending upon the analysis type, you may need to specify the following:

• Voltage on a net, a pin, or at a terminal of a semiconductor device
• Current through a part or into a terminal of a semiconductor device
• A device name

If output variables or other information are required, select Output File Options in the Monte Carlo/Worst Case dialog box and enter the required parameters.

Voltage

Specify voltage in the following format:

A fully qualified net name (as referred to in line 3 above) is formed by prefixing the visible net name (from a label applied to one of the segments of a wire or bus, or an offpage port connected to the net) with the full hierarchical path, separated by periods. At the top level of hierarchy, this is just the visible name.

A fully qualified device name (from line 4 above) is distinguished by specifying the full hierarchical path followed by the device’s part reference, separated by period characters. For example, a resistor with part reference R34 inside part Y1 placed on a top-level schematic page is referred to as Y1.R34 when used in an output variable.

A <pin id> (from line 4) is uniquely distinguished by specifying the full part name (as described above) followed by a colon, and the pin name. For example, the pins on a capacitor with reference designator C31 placed on a top-level page and pin names 1 and 2 would be identified as C31:1 and C31:2, respectively.

Current

Specify current in the following format:

i[modifiers](<out device>[:modifiers])

where <out device> is a fully qualified device name.

Modifiers

The basic syntax for output variables can be modified to indicate terminals of semiconductors and AC specifications. The modifiers come before <out id> or <out device>. Or, when specifying terminals (such as source or drain), the modifier is the pin name contained in <out id>, or is appended to <out device> separated by a colon.

Modifiers can be specified as follows:

• For voltage:
  v[AC suffix](<out id>[, out id]) v[terminal]*(<out device>)
• For current:
  i[AC suffix](<out device>[:terminal]) i[terminal][AC suffix](<out device>])

where

These building blocks can be used for specifying output variables as shown in Table 8-3 (which summarizes the accepted output variable formats) and Tables 8-4 through 8-7 (which list valid elements for two-terminal, three- or four-terminal devices, transmission line devices, and AC specifications).

The INOISE, ONOISE, DB(INOISE), and DB(ONOISE) output variables are predefined for use with noise (AC sweep) analysis.

Setting AutoConvergence

You can suggest relaxed limits for various options used for simulation. The PSpice engine can select one or more of the options with relaxed limits and change their values during the simulation to converge it.

To set the relaxed limits and specify autoconvergence:

1. From the Options tab of the Simulation Settings dialog box, click the Analog Simulation tree structure.
   
   
2. Select Auto Converge in the left panel.
3. Select the AutoConverge check box.
4. You can check the options for which you want to set relaxed limit and specify the limit value. For example, if the DC bias bind and iteration limit (ITL1) is set to 150, you can relax the value to 1000.

1. You can select the Restart option to pause PSpice A/D if convergence is not achieved at the end of the simulation time.
   
   Restart is selected by default.
2. Click OK.

When you run the simulation with AutoConvergence set, PSpice A/D initially runs using the normal values for the specified simulation time. However, if the simulation does not converge, PSpice A/D changes the values within the relaxed limit for the parameters selected in the Autoconvergence Option.

If convergence is not achieved at the end of the complete run, PSpice A/D starts simulation with an initial relaxed value if you the Restart option is selected.

You can specify the relative factor by which the minimum time step size is changed by setting the value of Relative factor for minimum delta (DMFACTOR) in the General node of the Advanced Analog tree structure. You can set any value that is a factor of 10 and is less than or equal to 1, such as .1, .001, or .0001. For example, if the default value of the minimum time step size is , you can specify DMFACTOR as .1. This will result in a minimum time step of .

Using Advanced Analog Options

You can use the Analog Advanced tree structure to set various Analog simulation parameters, which are useful to:

• Improve convergence for both bias point and transient analyses
• Assist debugging of convergence failure by printing simulation data
• Improve performance and remove overflow errors
• Control simulation parameters
• Improve accuracy of simulation results

The Analog Advanced tree structure displays default values for all the options and on checking some flag options - such as DIODERS, CSHUNT, BJTCJ, and DIODECJO, recommended values are also displayed.

Performance package

PSpice A/D includes two solution algorithms: Solver 0 and Solver 1.

To choose a solver setting

1. From the design entry tool’s PSpice menu, choose Edit Simulation Profile.
   or
   From the PSpice Simulation menu, choose Edit Profile.
   The Simulation Settings dialog box appears.
2. Click the Options tab, then click the Analog Advanced tree structure.
3. Select the General option in the Analog Advanced tree.
   
   
4. In the Solver drop-down list, select one of the following choices:
   • 0 - the PSpice simulation engine uses the original PSpice solution algorithm.
   • 1 - the PSpice simulation engine uses an advanced solution algorithm that provides significant speed improvements. This is default selection.
     Solver 1 is particularly useful for larger MOS and bipolar circuits with substantial runtimes.
5. Click OK.

See the PSpice A/D Reference Guide for .OPTIONSstatements that use SOLVER to specify a solution algorithm.

Starting a simulation

After you have used a design entry tool to enter your circuit design and have set up the analyses to be performed, you can start a simulation by choosing Run from the PSpice menu. When you enter and set up your circuit this way, the design entry tool automatically generates the simulation files and starts PSpice A/D.

There may be situations, however, when you want to run PSpice A/D outside of any design entry tool. You may want to simulate a circuit that was not created in Capture or Design Entry HDL, for example, or you may want to run simulations of multiple circuits in batch mode.

This section includes the following:

• Creating a simulation netlist
• Starting a simulation from a Design Entry Tool
• Starting a simulation outside of Design Entry Tool
• Setting up batch simulations
• The PSpice A/D simulation window

Creating a simulation netlist

A netlist is the connectivity description of a circuit, showing all of the components, their interconnections, and their values. When you create a simulation netlist from a design entry tool, that netlist describes the current design.

You have a choice between two types of netlist formats:

• a flat netlist
• a hierarchical netlist

The flat netlist is generated for all levels of hierarchy, starting from the top, regardless of whether you are pushed into any level of the hierarchy. Flat netlists are most commonly used as input to PCB layout tools. The flat simulation netlist format for PSpice A/D3 contains device entries for all parts on a subcircuit (child) schematic multiple times, once for each instance of the hierarchical part or block used.

The hierarchical netlist preserves the hierarchical information in any subcircuit (child) schematics. It contains a single .SUBCKT definition for each child schematic. The devices in the subcircuit are therefore netlisted only once. Each instance of the hierarchical part or block is then netlisted as an instance of that subcircuit (as an “X” device). The subcircuit name corresponds to the name of the subcircuit (child) schematic. Hierarchical netlists are especially useful to IC designers who want to perform Layout vs. Schematic (LVS) verification because they are more accurate descriptions of the true circuit. The hierarchical netlist format supports LVS tools such as Dracula.

Using netlisting templates

In OrCAD X Capture and Design Entry HDL, the PSPICETEMPLATE property specifies how primitive parts are described in the simulation netlist. It defines the pin order and which other part property values to include in the netlist. Only parts with a PSPICETEMPLATE property are included in the simulation. In the process of creating the netlist, buses, connectors, and so on, are resolved.

An alternate template option is provided which allows you to define which netlisting template property to use. This option applies to both flat and hierarchical netlists. With this option, you may specify a particular netlist template for generating netlists that can be used by other simulation tools, for example, or for creating alternate PSpice netlists that contain different part descriptions.

Running PSpice Netlister in Design Entry HDL

When you run the PSpice netlister in Design Entry HDL, the $PSPICE_LOCATION attribute is added to the components in addition to the $LOCATION attribute. To view $PSPICE_LOCATION, select the Display PSpice Names option of the PSpice Simulator menu.

The PSpice netlister makes intelligent decisions to create the attributes, under the following conditions:

New Design

If you run PSpice netlister in a new design, PSpice netlister generates both $LOCATION and $PSPICE_LOCATION.

Split Part

PSpice netlister combines the different sections of a split part and netlists them as a single instance based on the SPLIT_INST and LOCATION properties. The value of SPLIT_INST needs to be TRUE for a section to be recognized as belonging to a split part. The value of LOCATION identifies the sections belonging to one split part. Alternatively, the property SPLIT_INST_NAME can be used in place of the two properties SPLIT_INST and LOCATION. All sections of a split part needs to have the same value for SPLIT_INST_NAME if this property is used.

A requirement for netlister to be successful in recognizing split parts is that all sections should be in the same hierarchy level. However, the sections can be spread across different pages at the same level. In addition, the PSPICETEMPLATE property of each section must have the pins for all the sections of the split part.

The following conditions can result in either warning or an error:

• If PSPICETEMPLATE is missing from any of the sections, netlist is not created and an error message is displayed.
• If PSPICETEMPLATE has different values for the sections of a split part, netlist is not created and an error message is displayed.
• If one or more sections of the split part are missing, the pins of the missing part are treated as unconnected and a warning message is displayed.
• If one or more sections of a split part are instantiated more than one time, netlist is not created and an error message is displayed. This error is flagged only if the sec property from symbol.css has the same value for one or more parts of different instances.

Packaged Design

If you open a packaged design and run PSpice netlister, it will copy the $LOCATION values if they are unique and the RefDes prefix are same. If the prefix for RefDes for both $PSPICE_LOCATION and $LOCATION are different and the values do not exist, PSpice netlister will use the same prefix for both $LOCATION and $PSPICE_LOCATION. However, if the prefixes are same and the $LOCATION attributes are not unique, an error will be generated.

The following tables shows sample values of $LOCATION and $PSPICE_LOCATION when PSpice netlister is run.

Passing parameters to subcircuits

Hierarchical netlists have the advantage of allowing parameters to be passed from the top level schematic to any subcircuit schematics. To take advantage of this feature, you must use the new SUBPARAM part in the SPECIAL.OLB library in Capture and you must use the VHDL_DECS part in the STANDARD library in Design Entry HDL.

With the SUBPARAM part in Capture or the VHDL_DECS part in Design Entry HDL, you can pass parameters from the top-level schematic to a subcircuit schematic. This allows you to explicitly define the properties and default values to be used during netlisting and simulation.

To set up parameter passing to a subcircuit using SUBPARAM in Capture

1. Make the subcircuit your active schematic page in the Capture editor.
2. From the Place menu, choose the Part command.
3. Select the part SUBPARAM from the PSpice library SPECIAL.OLB and place it on the subcircuit.
4. With the SUBPARAM part still selected, from the Edit menu, choose Properties.
   The Property Editor spreadsheet appears.
5. In the spreadsheet, define the names and default values for the properties that can be changed on an instance-by-instance basis.
6. In the top-level schematic, use the Property Editor spreadsheet to edit the properties of the hierarchical part or block that references the subcircuit (child) schematic so they match the properties you defined in Step 5.

To set up parameter passing to a subcircuit using VHDL_DECS

1. Make the subcircuit your active schematic page in Design Entry HDL.
2. From the Component menu, choose Add.
   The Component Browser dialog box appears.
3. From the Library drop-down, select the STANDARD library.
4. From the Cells list, select the VHDL_DECS part and place it on the subcircuit.
5. From the Text menu, choose Attributes.
6. Click on the VHDL_DECS part to display the Attributes dialog box.
7. In the Attributes dialog box, define the names and default values for the properties that can be changed on an instance-by-instance basis. For example, to declare a parameter RFEEDBACK with the default value 1, do the following:
   1. In the Name text box, type RFEEDBACK
   2. In the Value text box, type 1\PARAM
8. In the top-level schematic, use the Attributes dialog box to edit the properties of the hierarchical part or block that references the subcircuit (child) schematic so they match the properties you defined in Step 7. Taking the example given in step 7, edit the properties of a block in the top-level schematic that references the subcircuit as below:
   1. In the Name text box, type RFEEDBACK
   2. To pass a parameter value 10 to the subcircuit, in the Value text box, type 10\PARAM

Any part in the subcircuit (child) schematic can reference the properties in its PSPICETEMPLATE. For example, in Design Entry HDL, if you want to pass the value of parameter RFEEDBACK from the block in the top-level schematic to a resistor in the subcircuit, do the following:

1. Make the subcircuit your active schematic page in Design Entry HDL.
2. From the Text menu, choose Attributes.
3. Click on the resistor to display the Attributes dialog box.
4. In the Value text box against the VALUE property, type {RFEEDBACK}.
   The parameter value 10 specified on the block in the top-level schematic will be passed to the resistor. The VALUE property is referenced in the PSPICETEMPLATE property of the resistor as below:

   R^@REFDES %1 %2 ?TOLERANCE|R^@REFDES| @VALUE ?TOLERANCE|\n.model R^@REFDES RES R=1 DEV=@TOLERANCE%|

The PSpice subcircuit mechanism supports parameterizing:

• constants specified on device statements
• model parameters
• expressions consisting of constants
• parameters
• functions

Creating the netlist

You can generate a simulation netlist in one of two ways:

• In capture, from Capture’s Project Manager by using the Create Netlist command under the Tools menu. (If this is the first time you’re creating a hierarchical netlist for this project, you can only use this method.)

- or -

• In both Capture and Design Entry HDL, directly from within the design entry tool itself by using the Create Netlist command under the PSpice menu. See Running PSpice Netlister in Design Entry HDL for information about running PSpice netlister from Design Entry HDL.

During the netlist process, the design entry tool creates several files with different extensions: the .NET file contains the netlist; the .CIR file contains simulation commands; and the .ALS file contains alias information.

To create a flat netlist from Capture Project Manager

1. In the Capture Project manager, select the design file (.DSN) you want to netlist.
2. From the Tools menu, choose Create Netlist to display the Create Netlist dialog box.
3. Select the PSpice tab.
4. Under the Options frame, leave all the check boxes blank.
5. In the Netlist File text box, type a name for the output file, or click the Browse button to assign a filename.
6. If desired, click the View Output check box to display the netlist after it has been generated.
7. Click OK.

To create a hierarchical netlist from Capture Project Manager

1. In the Capture Project manager, select the design file (.DSN) you want to netlist.
2. From the Tools menu, choose Create Netlist to display the Create Netlist dialog box.
   
   
3. Select the PSpice tab.
4. Under the Options frame, click Create Hierarchical Format Netlist.
5. Click Settings to customize the format of the hierarchical netlist (see Customizing the hierarchical netlist in Capture).
6. Click Create Subcircuit Format Netlist to specify how subcircuits will be netlisted (see Creating subcircuit netlists in Capture).
7. In the Use Template list box, select the netlisting template(s) you wish to apply (see Specifying alternate netlist templates in Capture).
8. In the Netlist File text box, type a name for the output file, or click the Browse button to assign a filename.
9. If desired, click the View Output check box to display the netlist after it has been generated.
10. Click OK.

For more information on netlist formats, refer to OrCAD X Capture Help.

Customizing the hierarchical netlist in Capture

You can customize the hierarchical netlist by specifying various options using the Settings button in the Create Netlist dialog box. You can also customize the format of the subcircuit definition and reference text in the netlist. These settings, once defined, will apply to all subsequent PSpice netlists whether the netlist is invoked from the Tools menu in the Project Manager or directly from the schematic editor.

Two groups of settings are saved: PSpice and LVS. Having two groups makes it easy to switch between netlisting for PSpice and netlisting for an LVS compatible format. You can specify which group of settings is active for the netlister by using the Products list box.

To customize the hierarchical netlist

1. In the PSpice tab of the Create Netlist dialog box, under the Options frame, click Create Hierarchical Format Netlist.
   
   
2. Click Settings, then enable or specify the following options, as desired:
   • Make .PARAM Commands Global: If this check box is enabled, any param parts in the design become global in scope. If it is disabled, the param parts are local to the subcircuit in which they occur.
   • Products: This list box specifies which group of settings is active for the netlister. Selecting a different group changes the Subcircuit Patterns frame to reflect the settings of the specified tool.
   • Global Net Prefix: This text box allows you to define the syntax of the global net of a subcircuit.
   • Reference frame
     • Subcircuit Call: This list box allows you to select the syntax of the subcircuit call using a modified TEMPLATE syntax.
     • ParamList Element Definition: This list box allows you to select the syntax of how parameters are passed from a reference to a part definition.
   • Definition frame
     • Subcircuit Header: This list box allows you to select the syntax of the subcircuit header using a modified TEMPLATE syntax. If modified, you must make sure the definition header is consistent with the call.
     • ParamList Element Definition: This list box allows you to select the syntax of how parameters are passed from a reference to a part definition.
     • Param Usage Reference: This list box allows you to select the syntax used to enclose the parameters in references.
     • Subcircuit Ends: This list box allows you to select the syntax used for the termination of a subcircuit.
   • Save as Project Default Settings: This button saves the current settings in the CAPTURE.INI file, and thereby makes the current settings the default settings for any new Capture projects.
3. Click OK.

For more detailed information about the syntax for these commands, and examples of how to use them, see the PSpice A/D Reference Guide.

Creating subcircuit netlists in Capture

You can specify how subcircuits in a hierarchical design are processed and defined in the simulation netlist.

To create a subcircuit format netlist

1. In the Capture Project manager, select the design file (.DSN) you want to netlist.
2. From the Tools menu, choose Create Netlist to display the Create Netlist dialog box.
3. Select the PSpice tab.
4. Under the Options frame, click Create Subcircuit Format Netlist, then click one of the following options, as desired:
   • Descend: This generates a definition of a hierarchical design that includes the top level circuit as well as its subcircuits. (This option is only available if Create Hierarchical Format Netlist is enabled.)
   • Do Not Descend: This generates a definition of a hierarchical design that includes only the top level circuit, without any of its subcircuits. (This option is only available if Create Hierarchical Format Netlist is enabled.)
   • Descend and Fully Expand: This generates a definition of a flat design. (This option is only available if Create Hierarchical Format Netlist is not enabled.)

Specifying alternate netlist templates in Capture

To specify an alternate netlist template

1. In the Capture Project manager, select the design file (.DSN) you want to netlist.
2. From the Tools menu, choose Create Netlist to display the Create Netlist dialog box.
3. Select the PSpice tab.
4. In the Use Template list box, select the name of the template you want to use.

By default, the netlister will use the PSPICETEMPLATE. Alternate templates in the Use Template list box will be processed in the order in which they appear. The ordering of the templates is therefore important to the netlister and determines what the output will be.

Use the control buttons located directly above the Use Template list box to configure the list of templates. You can:

• Add a new template by clicking the New icon or by double-clicking in the dashed box at the beginning of the list.
• Delete a template by selecting the name and then clicking the Delete icon.
• Edit a template name by selecting the name and then clicking the Edit icon.
• Change the order of the listing (move a template up or down in the listing) by selecting the name and clicking the Up or Down arrows.

Starting a simulation from a Design Entry Tool

After you have set up the analyses for the circuit, you can start a simulation from design entry tool in either of the following ways:

• From the PSpice menu select Run.
• Click the Simulate button on the PSpice toolbar.

Starting a simulation outside of Design Entry Tool

To start PSpice A/D outside of Capture

1. From the Start menu, point to the installed release, then choose PSpice.
2. From the File menu, choose Open Simulation.
3. Do one of the following:
   • Double-click on the simulation profile filename (*.SIM) in the list box.
   • Enter the simulation profile filename (*.SIM) in the File name text box and click Open.
4. From the Simulation menu, choose Edit Settings to modify any of the analysis setup parameters.
5. From the Simulation menu, choose Run (or click the Run toolbar button) to begin the simulation.

Setting up batch simulations

Multiple simulations can be run in batch mode when starting PSpice A/D directly with circuit file input. You can use batch mode, for example, to run a number of simulations overnight. There are two ways to do this, as described below.

Multiple simulation setups within one circuit file

Multiple circuit/ simulation descriptions can be concatenated into a single circuit file and simulated all at once with PSpice A/D. Each circuit/ simulation description in the file must begin with a title line and end with a .END statement.

The simulator reads all the circuits in the circuit file and then processes each one in sequence. The data file and simulation output file contain the outputs from each circuit in the same order as they appeared in the circuit file. The effect is the same as if you had run each circuit separately and then concatenated all of the outputs.

Running simulations with multiple circuit files

You can direct PSpice A/D to simulate multiple circuit files using either of the following methods.

Method 1

1. From the Start menu, point to the installed release, then choose PSpice.
2. Select Open Simulation from the File menu from the PSpice A/D window.
3. Do one of the following:
   • Type each file name enclosed in double quotation marks in the File Name text box separated by a space.
   • Use the combination keystrokes and mouse clicks in the list box as follows: Ctrl+click to select file names one at a time, and Shift+click to select groups of files.

Method 2

1. From the Start menu, point to the installed release, then choose PSpice A/D.
2. Update the command line in the following way:
   • Include a list of circuit file names separated by spaces.
   
   Circuit file names can be fully qualified or can contain the wild card characters (* and ?).

The PSpice A/D simulation window

The PSpice A/D Simulation Window is an MDI (Multiple Document Interface) application. This implies that you can open and display multiple files at the same time in this window. For instance, you can have a waveform file (.DAT), a circuit file (.CIR), and a simulation output file (.OUT) open and displayed in different child windows within this one window.

The PSpice A/D Simulation Window consists of three sections: the main window section where the open files are displayed, the output window section where output information such as informational, warning, and error messages from the simulator are shown, and the simulation status window section where detailed status information about the simulation are shown. These three sections are shown in Figure 8-1.

The windows in these sections may be resized, moved, and reordered as needed.

The simulation window also includes a menu bar and toolbars for controlling the simulation and the waveform display.

Title bar

The title bar of the simulation window (the area at the top of the window) identifies the name of the currently open simulation (either simulation profile or circuit file) and the name of the currently active document displayed in the main window area. For example, the simulation window shown in Figure 8-1 indicates that simulation profile SCHEMATIC1-Transient is currently open and the active document displayed is Transient.DAT.

Menus and Toolbars

The menus accessed from the menu bar include commands to set up and control the simulator, customize the window display characteristics, and configure the way the waveforms are displayed. The toolbar buttons duplicate many of the more frequently used commands.

Figure 8-1 PSpice A/D simulation window

Main window section

The top central portion (by default) of the simulation window is the main window section where documents (such as waveforms, circuit description, output information etc.) are displayed within child windows. These windows are tabbed by default. The tabs at the bottom left show the names of the documents that each child window contains. Clicking on a tab brings that child window to the foreground. Figure 8-1 shows the tabbed document windows for Transient.DAT and Transient.OUT.

You can configure the display of these windows to suit your preferences and to make the analysis of the circuit quick and readily understandable. These windows can also be resized, moved, and reordered to suit your needs.

Output window section

The lower left portion of the simulation window provides a listing of the output from the simulation. It shows informational, warning, and error messages from the simulation. You can resize and relocate this window to make it easier to read.

Simulation status window section

The lower right portion of the simulation window presents a set of tabbed windows that show detailed status about the simulation. There are three tabbed windows in this section: the Analysis window, the Watch Variable window, and the Devices window. The Analysis window provides a running log of values of simulation variables (parameters such as Temperature, Time Step, and Time). The Watch Variable window displays watch variables and their values. These are the variables setup to be monitored during simulation. The Devices window displays the devices that are being simulated.

Interacting with a simulation

PSpice A/D includes options for interacting with a simulation by changing certain runtime parameters in the course of the analysis. With the interactive simulation feature, you can do the following:

• Extend a transient analysis after TSTOP has been reached in order to achieve the desired results.
• Interrupt a bias or transient analysis, change certain runtime parameters, and then resume the simulation with the new settings.
• Schedule changes to certain runtime parameters so that they are made automatically during a simulation.

What the various versions of PSpice A/D support

The following table identifies what interactive functionality is available with each version of PSpice A/D.

Extending a transient analysis

Often, a long transient analysis will run to the completion time (TSTOP) without achieving the desired simulation results (achieving a steady state, for instance). To achieve better results, the value for TSTOP would have to be increased and the entire simulation would have to be rerun from the beginning. This was time-consuming and inefficient for large simulations.

A transient analysis will automatically pause rather than stop when it reaches the TSTOP value. Once paused, you can review the results and determine if the simulation should run longer. If desired, you can increase the value of TSTOP and resume the transient analysis from the point at which it paused, thus saving a good deal of processing time.

To help clarify under what conditions simulations will either be terminated or paused, the following table explains the different behaviors of PSpice A/D for particular simulation scenarios:

To extend a transient analysis

1. After you pause a transient analysis, click in the RunFor text box on the PSpice toolbar.
   
   
2. Enter a new value for TSTOP.
3. Click on the Run toolbar button to resume the simulation.
   The simulation will resume from the point at which it last paused, and then run for the amount of time specified in the RunFor text box, at which point it will pause again.

Interrupting a simulation

In PSpice A/D, you have the ability to interrupt (pause) a simulation, change certain runtime parameters, and then resume the simulation from the point at which it was paused using the new parameters.

When a simulation has been paused, you can change the following runtime parameters in the Edit Runtime Settings dialog box:

• • RELTOL
  • ABSTOL
  • VNTOL
  • GMIN
  • TSTOP
  • TMAX
  • ITL1
  • ITL2
  • ITL4

The PSpice Runtime Settings dialog box will appear automatically whenever a simulation fails to converge. (In such cases, the simulation will be paused automatically.) It will also appear if you attach PSpice A/D to a simulation that was paused in the background. (For more information about managing background simulations, see Using the Simulation Manager.)

To interrupt a simulation and change parameters

1. In PSpice A/D, from the Simulation menu, choose Edit Runtime Settings.
   The PSpice Runtime Settings dialog box appears.
2. If you want to use the original value for a particular parameter, click the Use Original Value check box for that parameter.
   The original parameter values are derived from the simulation profile. By default, the Use Original Value check boxes are checked (enabled).
3. If you want to change one or more parameters, enter new values for each of the runtime parameters you want to change in the text boxes under the column Change To.
   If a Change To text box is grayed out, uncheck the Use Original Value check box.
4. Click OK & Resume Simulation to resume the simulation with the new parameters.

Scheduling changes to runtime parameters

You may want to predefine a set of values for a parameter and schedule these values to take effect at various time intervals during a long simulation. For instance, you may want to use a smaller time step value during periods where the input stimulus changes rapidly, but otherwise use a larger value.

You can set up automatic changes to certain runtime parameters that will occur at scheduled times during a simulation. By scheduling the changes, you don't have to interrupt the simulation manually, and can even run it in a batch mode in the background.

The following runtime parameters can be changed at scheduled times during a simulation. Note that these only apply to transient analysis; you cannot interact with other analysis types.

• • RELTOL
  • ABSTOL
  • VNTOL
  • GMIN
  • ITL4

PSpice command syntax for scheduling parameter changes

You can schedule parameter changes by entering them either in the Maximum Step Size text box in the Simulation Profile or in a text file using the new expression SCHEDULE, and then including that file in the simulation profile settings.

The expression SCHEDULE is a piecewise constant function (from time x forward use y) and takes the form:

SCHEDULE(x1,y1,x2,y2…xn,yn)

where x is the time value, which must be x >= 0, and y is the value of the associated parameter. You must include an entry for time = 0.

When used with the .OPTIONS command, the syntax is as follows:

.OPTIONS <Parameter Name>= {SCHEDULE(<time-value>, <parameter value>, <time-value>, <parameter value>, …)}

For example,

.OPTIONS RELTOL={SCHEDULE( 0s,.001,2s,.005)}

indicates that RELTOL should have a value of 0.001 from time 0 up to time 2s, and a value of 0.005 from time 2s and beyond (that is: RELTOL=.001 for t, where 0 <= t < 2s, and RELTOL=.005 for t, where t >= 2s).

To schedule changes to runtime parameters

1. Open a standard text editor (such as Notepad) and create a text file with the command syntax shown above, using the appropriate values for the different parameters.
2. In Capture, open the design you want to simulate.
3. From the PSpice menu, choose Edit Simulation Profile.
   The Simulation Settings dialog box appears.
4. Click on the Configuration Files tab
5. Click Include in the Category field to display the Include files list.
6. Under the Filename text box, enter the name of the text file you created in Step 1, or click the Browse button to locate the file and enter the full path and filename.
7. Click the Add to Design button to include the file as part of the circuit.
8. Click OK.
   When you run the simulation, the scheduled parameter changes will be included as part of the circuit file and the simulation will run to completion automatically.

Setting Autoconvergence from the Runtime Settings Dialog Box

The RunTime Settings dialog box allows you to set autoconvergence options during a simulation run. From this dialog box, you can select:

• Autoconvergence
• Enable Advanced Convergence Algorithms

To enable autoconvergence:

1. Select Autoconvergence.
2. You can either use the default relaxed limits for parameters or click Settings and change the limits.
   
   Refer to Setting AutoConvergence for information on the limits in autoconvergence.

To enable advanced convergence algorithms:

1. Select Transient and Bias Point options in the Analog Advanced tree structure of the Options tab.
2. Set the options.

The options are enabled according to the running simulation. For example, in the Bias Point mode, the GMIN, Source-stepping and Pseudo-Tran options are available, while in the Transient mode, the TRTOL and METHOD options are available.

Using the Simulation Manager

Overview of the Simulation Manager

PSpice A/D includes a new Simulation Manager that provides enhanced control over how multiple simulations are processed. You can preempt the current simulation to run another one first. Or, you can use the Simulation Manager to monitor the progress of a set of batch simulations that were set up and launched earlier.

The PSpice Simulation Manager provides a familiar, easy-to-use interface for controlling how multiple simulations are processed.

The Simulation Manager allows you to do the following:

• add or delete simulations
• start, stop or pause simulations
• rearrange the order of the simulations in the queue
• attach PSpice to a simulation to make it the active display
• view the status and progress of simulations running in the background

You can accomplish most of these functions by selecting the desired simulation in the list, then clicking on the appropriate toolbar button to execute the command.

Accessing the Simulation Manager

The Simulation Manager is invoked whenever you start a new simulation, either from PSpice A/D or from a front-end design entry tool. Since it is active as long as a simulation is running in the background, you can also call up the Simulation Manager from the Windows system tray.

You can also launch the Simulation Manager by itself from the Windows Start menu. You do not need to have PSpice A/D running in order to work with the Simulation Manager.

Understanding the information in the Simulation Manager

Every job listed in the Simulation Manager will have a specific entry for Schedule, Status and Percent Complete. In addition, certain color-coded icons are shown to the left of each simulation file name to indicate their current state. A quick glance over the list of jobs will tell you immediately where any particular job is and how it will be processed. The following tables explain the meanings of the various categories and states.

What the various versions of PSpice A/D support

The following table identifies what functionality in the Simulation Manager is available with each version of PSpice A/D.

How the Simulation Manager handles errors during simulation

Since each simulation that runs in the background runs independently, an error that occurs during one simulation will not prevent the remaining jobs in the queue from running subsequently, in order. The following common error conditions may arise, but these will not prevent the Simulation Manager from running the remaining simulations pending in the queue.

Simulation crash: If a simulation crashes for whatever reason, the Simulation Manager will stop receiving progress updates. After a certain period, the Simulation Manager will stop that simulation and will automatically start the next job in the queue.

Simulation pause: If a simulation pauses automatically and requires manual intervention to continue, the Simulation Manager will automatically start the next job in the queue.

Simulation stop: If a simulation stops automatically, the Simulation Manager will automatically start the next job in the queue.

Setting up multiple simulations

With the Simulation Manager, you can set up any number of batch simulations to be run sequentially in the background while you do other work in PSpice A/D. Each new simulation that you set up will be added to the bottom of the simulation queue and will be assigned the schedule category “queued”. It will be run after all other queued jobs ahead of it have been run.

Once a job has been added, you can change its position in the queue, start, stop or pause it, or make other modifications to its status.

To add a simulation to the queue

1. From the File menu, choose Add Simulation or click the Add Simulation button on the toolbar.
2. Locate the file (.SIM, .CIR) you wish to add to the queue.

Alternately, you can add a simulation to the queue by starting the PSpice simulation directly from within the front-end tool you are using, such as OrCAD X Capture.

Starting, stopping, and pausing simulations

In the Simulation Manager, you can easily manage the various batch simulations in the queue. The most fundamental controls that are provided are the ability to start a simulation, stop it, or pause it temporarily.

To start a simulation from the Simulation Manager

1. Select a simulation in the list.
2. From the Simulation menu, choose Run or click the Run Selected button on the toolbar.

To stop a simulation from the Simulation Manager

1. Select the simulation that is currently running.
2. From the Simulation menu, choose Stop or click the Stop Selected button on the toolbar.

To pause a simulation from the Simulation Manager

1. Select the simulation that is currently running.
2. From the Simulation menu, choose Pause or click the Pause Selected button on the toolbar.

Attaching PSpice A/D to a Simulation

A simulation that is running in the Simulation Manager will not be loaded into PSpice A/D or displayed in Probe while it is running. This allows you to work on a different design in the PSpice A/D application while a simulation is running in the Simulation Manager.

If you want to display a different simulation in PSpice A/D by choosing from the list of jobs in the Simulation Manager, you can attach PSpice A/D to a particular job in the queue.

To attach PSpice A/D to a simulation, do the following steps:

1. Select the simulation you want to attach PSpice A/D.
2. From the View menu, choose Simulation Results.
   The PSpice A/D program will activate and the results of the simulation you selected will become the current display in Probe. If the simulation is currently running, you will be able to view the marching waveforms.

Setting options in the Simulation Manager

Each time you add a new simulation while another is running, the Simulation Manager must decide how to treat the new job. The default setting is to add the new simulation to the bottom of the queue and continue running whatever job is currently being simulated.

You can change this default so that the Simulation Manager will start each new simulation immediately and either stop or pause whatever job is currently running. The options you can choose from are explained in the procedure below.

You can also choose to have the Options dialog box display each time you add a new simulation, or not show this anymore. If you disable the prompting, you can always enable it again using the following procedure.

In addition, you can define how paused simulations should be handled by the Simulation Manager. You can configure them to be resumed automatically after the previous simulation stops, or you can choose to leave them in a paused state until you manually resume them.

To set the default options for the Simulation Manager, do the following steps:

1. From the Tools menu, choose Options.
   The Options dialog box appears.
   
   
   
2. In the top frame dealing with simulations that are already running, click the appropriate radio button for the option you wish to set.
   

   Radio button	Function
   Display the simulation in the queue.	The simulation that is currently running will be displayed in PSpice. The new simulation will be added to the bottom of the queue and will be run after all other jobs in the queue have been run. (This is the default setting.)
   Pause the current simulation and run the new one.	The simulation that is currently running will be paused. The new simulation will be started immediately. You must remember to resume the paused simulation later if you want it to continue.
   Stop the current simulation and run the new one.	The simulation that is currently running will be stopped. The new simulation will be started immediately. You must remember to restart the stopped simulation later if you want it to run again.

3. If you want the Options dialog box to appear as a reminder each time you add a new simulation, be sure to check the Always Prompt box. (The default setting is to enable this feature.)
4. In the bottom frame dealing with paused simulations, click the appropriate radio button for the option you wish to set.
   

   Radio button	Function
   Resume simulating.	The first paused simulation in the list will automatically resume after the previous simulation has stopped. (This is the default setting.)
   Wait for user intervention.	The Simulation Manager will not resume any paused simulations automatically. You must intervene manually to resume them. If you enable this radio button, you must remember to intervene manually if you want paused simulations to resume later.

5. Click OK to save the settings.

1. Depending on the license available, you will access either PSpice A/D or PSpice Simulator.
2. In this guide, design entry tool is used for both OrCAD X Capture and Design Entry HDL. Any differences between the two tools is mentioned, if necessary.
3. Depending on the license available, you will access either PSpice A/D or PSpice Simulator.