DDR Routing Techniques in Your PCB Design

Watching a child learn to tie their shoes can be a frustrating experience for the parent. Laces end up going everywhere and eventually tangling together until ultimately you are left dealing with a great big knot. Sometimes it’s tempting to resolve the problem by grabbing a pair of scissors. But when the child finally succeeds and ties their shoes correctly for the first time, it is a moment of celebration.

Sometimes routing a printed circuit board can feel the same way. When first laying out a PCB design, the tangled mess of nets going everywhere can seem like the same old battle of the shoe laces – except that now there are 2,000 pairs of shoes to deal with. The goal then is to get to that moment of exhilaration where the routing is completed, and done correctly. This can be more complicated than you would think though when it comes to high speed memory routing. Let’s take a look at some of the DDR routing techniques that will help you.

The Importance of DDR Routing Techniques

Double-Data Rate, or DDR memory is very common in printed circuit board design today. Many designs will use some version of this memory configuration which requires specific routing patterns in the layout. DDR gets its name from its ability to send and receive signals twice per clock cycle, which is double the rate of the original Single Data Rate (SDR) memory. Because of this doubled rate, the trace routing for DDR memory must hold tighter parameters in order to meet the performance specifications.

The key to designing memory circuitry is in meeting its timing specifications. Each signal needs to be timed so that the data can be captured on the rising and falling edge of the associated clock signal. As the data rates increase with each new iteration of DDR memory, the timing margins will become narrower. This is where precise routing patterns are needed in order to fulfill the timing requirements.

Serpentine routing like this is important when tuning DDR routing for match lengths

There’s More to This then Just Routing Traces

Before you can start laying down traces in your DDR design, you still need to follow the basic principles of high speed design in your placement. This includes placing your parts to recreate the signal paths defined on the schematic, and keeping sensitive high speed circuitry isolated from other circuitry that could potentially cause interference. You will also want to give yourself enough room in your placement for DDR routing channels and pin escape routing. At the same time you need to place memory chips close together and locate them sequentially starting with the lowest data bit chip first and ending at the highest.

Another area of layout that will require attention in your DDR design is in designing the power delivery network. Reference voltages can play a very critical role in the signal integrity of your memory routing. Incorrect reference voltages can cause false triggering of your signals, and therefore will require proper filtering to hold their specified levels. This means adding bypass capacitors to stabilize your power network which will take up additional room in your placement.

Routing Considerations for DDR Circuitry

As we said earlier, the critical point to DDR circuitry is in the timing. This means that the clock lines will determine the timing of the input and output of the memory chip data lines. Electrical signals can not be sped up, so the only way to control the timing is to add length to the traces in order to delay the arrival of the clock signal. This is accomplished by adding serpentine routing to the trace routing. By adjusting the arrival time of the clock signal, the data lines can then be similarly adjusted so that each bit of data arrives and stabilizes before the next clock cycle.

There are two different routing methodologies that are often used for routing DDR circuitry, T-topology and fly-by topology:

• The T-topology methodology routes the command, address, and clock signals from the controller to the memory modules in a branch fashion while the data lines are directly connected. This methodology was originally adopted for DDR2, but couldn’t handle the higher signaling rates of DDR3 and DDR4. The branching was a challenge to route, but had the advantage of being able to handle the higher capacitance loads of multi-die packages.

• The fly-by topology routing is more of a daisy chain topology that routes the command, address, and clock signals in a chain from the controller to the memory modules. Again, the data lines connect directly between the controller and the memory modules. This methodology supports higher frequency operations by reducing the amount of trace stubs from T-topology, which also improves its signal integrity. The daisy chain structure of fly-by topology is also easier to route then the branching structure of T-topology.

The key to timing all of these lines together is to use trace length tuning and trace length matching in your routing. The DDR traces will only perform as expected if the timing specifications are met. These specifications can be found in datasheets, and you should set your high speed design constraints to hold these length specifications.

Another important factor to keep in mind is that which layer of the board you are routing on will also make a difference in your routing. Inner layer routing (stripline) will have different performance characteristics than outer layer routing (microstrip), which will affect the speed of the signal. The tuning of traces on inner and outer layers can not simply be matched, they must be adjusted to account for the different layer characteristics as well. Additionally, as signal timing becomes more critical with each new version of DDR, the entire time-of-flight (TOF) needs to be considered in your total overall signal path length for matching. This means including internal package lead dimensions into trace length calculations as well.

Advanced PCB design tools like Cadence Allegro can make a difference with complex layouts

The Future is Now

We’ve seen DDR memory capabilities and the PCB trace routing to support it steadily advance through the years to its current technology level of DDR4. Now we are about to enter the next phase of memory advancement with DDR5. With base speeds of DDR5 doubling that of DDR4, the routing specifications will likely be tighter yet. To stay on top of this advancing technology, PCB designers need layout tools that can handle the new challenges that they will encounter. They will need the ability for flow planning of DDR routing along with advanced trace length matching and tuning capabilities built into their PCB design tools.

The PCB design tools from Cadence can give you the power and performance that you need for designing these advanced DDR routing methodologies. Allegro PCB Designer has the constraint driven process that can simplify setting up these DDR routing topologies so that you can get on to the important business of designing your board.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.