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Dual In-line Package (DIP) IC: It Lives!

Key Takeaways

  • How DIP technology operates within the dominant SMT manufacturing mode.

  • The basics of DIP: naming, pinout, and more.

  • Common DIP variants and the fingerprints it's left on today’s packages.

View of multiple DIP ICs.

The dual in-line package (DIP) IC remains a favorite for legacy chips and prototyping.

Looking back at technology over the years gives people a profound sense of progress; it’s hard not to look at the early iterations of humanity’s most critical inventions and feel a sense of nostalgia for the germs that later develop into everyday indispensables. The 20th century was marked by a great deal of innovation – the automobile, the airplane, the internet – yet increasingly at the core of all of these are the PCBs and components that extend their functionality, in many cases indispensably so. Unlocking the potential of semiconductor devices ushered in the solid-state era of electronics in the second half of the 20th century, and even within a scant few decades the industry would rapidly evolve with breakthroughs in research and manufacturing efficiency. But much like the forgotten cat’s whisker detector that pushed semiconductors to the forefront over vacuum tube technology, there is still immense use for many of the depreciated technology formats and structures that have fallen by the wayside.

The dual in-line package (DIP) IC is a perfect example: once the standard for ICs in the late-20th century, it was rapidly replaced with the advent of surface mount technology (SMT). However, there remains significant use of legacy chips that retain the format for prototyping and product development.

Common DIPs by the Numbers

Pitch (inches/mm)

Row spacing (inches/mm)

Pin number



8, 14-24


24, 28, 32, 36, 40, 48, 52

.4/10.16, .9/22.86



.3/7.62, .6/15.24, .75/19.05


How the Dual In-line Package (DIP) IC Survived SMT

Electronics have drastically decreased in form factor over the past decades. The driving development is continual reductions in semiconductor process nodes, but the package itself has also allowed for greater functionality in smaller housings. The adoption of SMT in the 90s would displace through-hole packaging due to the smaller overall package size and reduction of associated drilling costs. However, some common through-hole packages have survived despite being less suitable for modern electronic assemblies, with the DIP finding a niche as a favorite for board prototyping and programable hardware.

While DIP packages were a prevailing style starting in the 70s until the 90s (many of the legacy chips of this era can still be purchased today in the DIP format) the greater manufacturing efficiency afforded by SMT makes current-day production of DIP economically infeasible for modern product lines. To counter this, chip manufacturers have designed interfacing devices for SMT components that allow them to be used analogously to DIP in prototyping.

As a converse to the SMT-DIP interface for prototyping, DIP sockets provide an alternative assembly method that supports in-circuit prototyping and thermally sensitive components. A select socket is soldered to the board during standard processes which then allows for placement of a DIP with corresponding pitch and row spacing. Because the chip is not fused to the board with a solder joint, removal and replacement are possible for iterative prototyping while the reduced adherence between board and component is of minimal concern during product development. Sockets themselves can use through-hole interfaces or bond to the board with SMT pads, with the latter usually supporting zero-insertion force design that makes for easier mating cycles between DIPs and sockets at the cost of less reliable connections, additional assembly space, and cost.

Working With DIP: Package Names, Pinout, and Orientation

The DIP naming convention is easy to understand at first glance: two rows of parallel pins extend downward from a rectangular package body. The most common pin count for the package is fourteen (the PINs of a DIP can be written after the acronym, i.e. DIP14), but other pinouts can be as low as eight or as high as sixty-four. DIP pin numbering is fairly simple, with a notch in the package functioning as a visual orientation element (for both humans and machines) that will indicate pin 1 as the top left lead when the notch is at the top of the package. Enumeration continues counter-clockwise around the package, with the important wrinkle that a package omitting pins will number the pins as if the omitted pins were still present.

DIP Variants for Specialization and the Continued Impact of DIP

Bottom-side view of pin grid array package.

The pin grid array (PGA) is an intermediate form between the DIP and modern ball grid array (BGA).

The former popularity of DIP led to numerous variant models that prioritize material construction or space savings/pinout density:

  • Single in-line package (SIP) - A removal of a pin row results in a package with a smaller footprint and per-unit cost. The missing row of pins can also be replaced with a tab for interfacing with a heat sink, allowing for greater power parameters.

  • DIP - 

    • Plastic dual in-line package (PDIP) - The cheapest DIP material option, which can have considerable savings in dense, high-volume assemblies.

    • Ceramic dual in-line package (CDIP) - Ceramic packages supported erasable programable read-only memory (EPROM) with a clear quartz window that could erase the chip die with ultraviolet light. One-time programable (OTP) PDIP models of these lines were also available, with both functioning as early microcontrollers and BIOS ROM.

    • Shrink/skinny dual in-line package (SDIP/SPDIP) - Shrink and skinny DIPs refer to different space-saving options: shrink reduces pin pitch by 30% while skinny halves the row spacing.

  • Quad in-line packaging (QDIP) - Adds two additional rows to each side of the DIP. These staggered rows improved the solderability and routeability of single-sided PCBs during the heights of DIP manufacturing. 

Even with the general depreciation of through-hole technology in modern electronics, the impact of the DIP still lives on in many modern SMT packages. The extremely popular small outline integrated circuit (SOIC) family of packages is a mainstay of modern devices that significantly reduced the pitch, footprint, and height of the component compared to DIP. The SOIC style shrinks pitches to half that of DIP, with small-outline packages (SOP) further reducing the pitch by a factor of two. Additionally, the gull-wing or J-type leads common to these components significantly eases fabrication costs and complexity through SMT. The ball grid array (BGA), which is the pinnacle of component density/miniaturization, also can trace its lineage back to the DIP: the pin grid array (PGA) that preceded the BGA before the onset of SMT was designed around the pitch of the DIP. 

Cadence Offers Electronic Systems Solutions from Chip to Board

Dual in-line package (DIP) ICs may not be as relevant today as they once were during their peak, but they still hold a prominent role in prototyping and legacy product lines. As with other through-hole packages, assembly density constraints and fabrication costs have seen DIP packages fall out of favor, but product development should be aware of how and when to integrate DIPs into PCB production for applicable cases. Design isn’t always so cut-and-dry, however, and engineers may find existing options lacking or needing further customization.  Fortunately, system development has a new solution in the first-of-its-kind Allegro X Design Platform: a complete design environment for PCBs down to logical/physical implementation. With the Allegro X Advanced Package Designer, design teams can layout chips using the same thermal and signal integrity analysis tools they’ve grown accustomed to at the board level.

Leading electronics providers rely on Cadence products to optimize power, space, and energy needs for a wide variety of market applications. To learn more about our innovative solutions, talk to our team of experts.