Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 20 Results: Default Physical CSet copied to PCS_CSET1 with: o Conductor Layers: Min Line Width=6 mil and Neck Width=4 mil o Plane Layers: Min Line Width=12 mil and Neck Width=6 mil Default Physical CSet copied to PCS_CSET2 with: o Conductor Layers: Min Line Width=10 mil and Neck Width=8 mil o Plane Layers: Min Line Width=15 mil and Neck Width=10 mil Rule Set name with prefix "PCS_" added to the new Physical CSet name Note: Multi-Row Header "Rule=" designation marks the beginning of a Rule Set with all Constraint columns included in it until another "Rule=" designation is seen. Rule MY_RULES Revision 1 Units mil Created by Cadence Header Layer Type Width:Min Line Line To Line Max Length Data 6 8 127mm End