Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 74 Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1) This lab will cover the creation of a Net Group and Diff Pairs in support of a DDR3 Interface. Diff Pair, Physical, and Diff Pair rules will be defined as well as Spacing Class-to-Class rules between Virtex-7 and the DDR3 SODIMM Connector. These will be design-specific tables referencing pre-defined Physical and Spacing Rule Specifications. 1. Reopen the ACC_start.brd file in the Layout Editor. (You will start fresh for every lab.) 2. Type the following on the Command Line: (load("skill.il")) This will load the required SKILL Routine to calculate the BITS of each Bytelane. The plan is to build this type of function into ACC by default, but for now, you need to load the simple SKILL Routine to assist in the Bytelane creation.