Allegro PCB Designer RAKs

Allegro Constraint Compiler

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Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 19 Column Header Descriptions Rule Specificatio n Type Rule, PhysicalRule, SpacingRule or ElectricalRule (Cell A1) Layer Type or Layer Index Layer Type = Conductor or Plane or Generic Layer Name "Conductor/External" Layer Index = Layer Number Rule= Rule Set name referenced in other tables Rule Specification Name:Rule Set Name or Rule Specification Name. Removing Rule Name (blank cell) will place all constraints in one Rule Set name based on the Rule Specification name Multiple Rule Specifications or Constraint Sets from different domains can be listed separated by a semicolon ";" Constraint Name Constraint Attribute name (MIN_LINE_WIDTH, LINE_TO_LINE_SPACING, MAX_VIA_COUNT) Note: Hovering over the header in Constraint Manager will report the Constraint Attribute name in the Datatip. Note: Custom Keyword mapping defined in the Directive Global section of CDS_ACC_DIRECTIVES.CSV (Cadence Default) or ACC_DIRECTIVES.CSV (User Defined) Rule Specification Table (Rule Sets) Examples: PhysicalR ule MY_PHY_RUL ES Revision 1 Units mil Created by Cadence Header Layer Type Rule=CSET1 Rule=CSET2 Width:Min Line Width:Neck Width:Min Line Width:Neck Data Conductor 6 4 10 8 Plane 12 6 15 10 End

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