Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 35 ACC Lab Exercises License Requirements / Workshop Structure ACC requires one of the following product licenses: o Allegro PCB Designer with the High-Speed Option o Allegro Venture PCB Designer Suite o Allegro Enterprise PCB Designer Suite o Allegro Package Designer + (Packaging) o Allegro Design Authoring (Schematic) Workshop directory structure: File/Folder Description acc_library Folder with starter ACC template files for completion during the labs compiler Local project ACC Configuration file folder, ACC_Directives.csv ACC_start.brd Workshop database ACC_START.color Color View file to return layer display and zoom back to default view ACC_Workshop_mapping.xlsx Start ACC Mapping table completed during the labs skill.il SKILL Routine required to complete Lab 9 and 10; the labs contain instructions on how to load the file for use. This routine is used to calculate the required BITS for each Byte lane in a DDR Memory Interface. LANE0 = DQ0,DQ1,DQ2,DQ3,DQ4,DQ5,DQ6,DQ7 LANE1 = DQ8,DQ9,DQ10,DQ11,DQ12,DQ13,DQ14,DQ15 … The plan is to build this type of function into the compiler by default, but for now, this simple SKILL Routine should be loaded/updated to assist in Byte lane creation. ACC_Golden_Data.zip Backup ZIP of all workshop files to quickly restore the original and unmodified files acc_workshop_COMPLETE Duplicate workshop structure with completed: ACC templates (acc_library) ACC Mapping table (ACC_Workshop_mapping.xlsx) Note: Workshop should be started in this folder when skipping ACC table creation during labs.