Allegro PCB Designer RAKs

Allegro Constraint Compiler

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Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 21 Results: Excluding the Rule column header places all rules in one Constraint Set by domain. Leaving the Layer Type applies Physical and Spacing rules on all layers. Default Physical CSet is copied to PCS_MY_RULE with Min Line Width of 6mil. o Rule Specification with prefix "PCS_" added to the new Physical CSet name Default Spacing CSet is copied to SCS_ MY_RULE with Line To Line spacing of 8 mil. o Rule Specification with prefix "SCS_" added to the new Spacing CSet name Electrical CSet ECS_MY_RULE is created with Total Etch Length Max set to 127mm. o Rule Specification with prefix "ECS_" added to the new Electrical CSet name o Note: Default units for all values are specified in the header, but different units can be entered in any cell which will be converted to the correct units.

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