Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 79 Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35) This lab will cover the creation of a Net Group and Diff Pairs in support of a DDR3 Interface. Diff Pair, Physical, and Diff Pair rules will be defined as well as Spacing Class-to-Class rules between the Viper ASIC and the On-Board DDR3 memory BGAs. This will represent a central library reuse model where Object and Object Rule tables contain alias variables that will be substituted using a design-specific Mapping table. 1. Open the ACC_start.brd file in the Layout Editor. 2. Type the following on the Command Line: (If you have not done so for this session) (load("skill.il")) This will load the required SKILL Routine to calculate the BITS of each Bytelane. o The plan is to build this type of function into ACC by default, but for now, you need to load the simple SKILL Routine to assist in the Bytelane creation.