Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 39 Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1) This lab will cover the creation of a Net Group with Physical, Spacing, and Electrical rules for the Protocol Analyzer bus between Virtex-5 and Virtex-7 BGAs. These tables will be design specific, with no library data dependencies. 1. Reopen the ACC_start.brd file in the Layout Editor. (You will start fresh for every lab.) To perform this workshop with already-completed ACC tables, open the database from the acc_workshop_COMPLETE folder. Review the steps below using the completed tables; then continue to Step 10 to "Open Constraint Manager". 2. Open the starter Rule Specification file in the Lab-2_Virtex-5_to_Virtex-7 folder. rule_spec_Proto_Analyzer.xlsx 3. Enter the following in the table: Rule name PPC_A_RULES / Interface name PPC_A / Units as mil Leave the Layer Type column on the Data row blank