Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 46 Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2) This lab will cover the creation of three Net Groups with Propagation Delay rules for the Host Port bus between Virtex-7 and the DSP BGA. These will be design-specific tables referencing pre-defined Physical and Spacing Rule Specifications. 1. Reopen the ACC_start.brd file in the Layout Editor. (You will start fresh for every lab.) To perform this workshop with already-completed ACC tables, open the database from the acc_workshop_COMPLETE folder. Review the steps below using the completed tables; then continue to Step 10 to "Open Constraint Manager". 2. Open the starter Object table in the Lab-4_Virtex-7_to_DSP folder: object_grouping_Host_Port.xlsx 3. Enter the following information in the table: Object name VIRTEX-7_TO_DSP and Interface name Host Port Update the other information in the header as required.