Allegro PCB Designer RAKs

Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 36 Lab 1-1: Rule Specifications Structure Review This lab will review the Rule Specifications structure and how they can be stored in a central library for use on many designs. Start template files (.xlsx) will be provided as part of the installation. 1. Navigate to the acc_library/Lab-1_Rule_Spec_Sets folder. These files are Constraint Set equivalents for ACC. Save as a CSV file and ACC will compile them into the associated Constraint Sets in the Layout Editor. 2. Open Phy_Spc_Rule_Sets.xlsx. Notice multiple Rule Specification tables (PHY, PHY_LAYER, SPC) referencing multiple Rule Sets (Rule=). This template file contains several tabs to store Data Row Examples as well as quick reference tabs for Physical, Spacing, and Electrical Constraints column names. The PHY Rule Specification calls out Physical rules for all layers in the design indicated by the Layer Type column being . The PHY_LAYER Rule Specification calls out Physical rules by per pre- defined Generic Layer Types (Constraint Column in Cross Section Editor). The SPC Rule Specification calls out Spacing rules for all layers in the design indicated by the Layer Type column being . A Rule= callout in the header row describes the beginning of the Rule Set with the following columns to the right of it being include in the Rule Set until another Rule= column in seen.

• Cover
• Purpose
• Audience
• Terms
• Overview
• Benefits of ACC
• Functional Overview
• Table and Specification Format Overview
• Mapping Name Table
• Object Table
• Rule Specification Table (Rule Sets)
• Object Rule Table (Object Rules)
• Object Rule Table (Class-to-Class Rules)
• User Interface and Data Query
• Validation and Apply Constraints to Design
• Reporting
• ACC Lab Exercises
• License Requirements / Workshop Structure
• Lab 1-1: Rule Specifications Structure Review
• Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1)
• Lab 1-3: DSP (RefDes U2) To HS Connector (RefDes U4)
• Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2)
• Lab 1-5: VIRTEX-7 (RefDes U1) To PCIe HSIO (RefDes J3)
• Lab 1-6: Viper (RefDes U34) To PCIe CONN (RefDes J1)
• Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional
• Lab 1-8: Viper (RefDes U34) To SATA Connectors (RefDes J2,J7-9,J11,J12)
• Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1)
• Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35)
• Support
• Feedback