Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 62 Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional This lab will cover the creation of 2 Net Groups and 16 Diff Pairs with Diff Pair and Spacing Class-to-Class rules for a PCIe bus between Viper ASIC and the Virtex-7. This will represent a central library reuse model where Object and Object Rule tables contain alias variables that will be substituted using a design-specific Mapping table. 1. Reopen the ACC_start.brd file in the Layout Editor. (You will start fresh for every lab.) To perform this workshop with already-completed ACC tables, open the database from the acc_workshop_COMPLETE folder. Review the steps below using the completed tables; then continue to Step 14 to "Open Constraint Manager". 2. Open the starter design-specific Mapping table in the main design folder: ACC_Workshop_mapping.xlsx