Allegro PCB Designer RAKs

Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 34 Reporting Both "Validate" and "Apply Constraints to Design" will generate and present a report that contains all warnings, errors, and changes that were made (or will be made). Select the side panel to expand each of the loaded specifications to see the updates.

• Cover
• Purpose
• Audience
• Terms
• Overview
• Benefits of ACC
• Functional Overview
• Table and Specification Format Overview
• Mapping Name Table
• Object Table
• Rule Specification Table (Rule Sets)
• Object Rule Table (Object Rules)
• Object Rule Table (Class-to-Class Rules)
• User Interface and Data Query
• Validation and Apply Constraints to Design
• Reporting
• ACC Lab Exercises
• License Requirements / Workshop Structure
• Lab 1-1: Rule Specifications Structure Review
• Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1)
• Lab 1-3: DSP (RefDes U2) To HS Connector (RefDes U4)
• Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2)
• Lab 1-5: VIRTEX-7 (RefDes U1) To PCIe HSIO (RefDes J3)
• Lab 1-6: Viper (RefDes U34) To PCIe CONN (RefDes J1)
• Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional
• Lab 1-8: Viper (RefDes U34) To SATA Connectors (RefDes J2,J7-9,J11,J12)
• Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1)
• Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35)
• Support
• Feedback