Allegro PCB Designer RAKs

Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 18 In most cases, Physical and Spacing Constraint Sets are closely related, with only a couple of changes for special conditions or circumstances. To avoid having to enter all possible constraints in the Rule Specification, the DEFAULT Physical and Spacing Constraint Sets in Constraint Manager will be used as a starting point with only the constraints entered in the table updated. The compiler will determine which Constraint Set Type (domain) to be created based on the entered rules in the Rule Specification. For example: Entering "Width:Min Line", "Line To Line", and "Max Length" in one Rule Specification will generate Physical, Spacing, and Electrical Constraint Sets for the three different constraint types. In support of rules which can be present in multiple domains, the Rule Specification type can be updated to include the target domain (prefix to Rule): "PhysicalRule,

(Physical domain) "SpacingRule, (Spacing domain) "ElectricalRule, (Electrical domain) Note: One example of this is Differential Pair rules that can be defined in the Electrical domain (all layers' rules) and Physical domain (layer-specific rules). A Rule Specification can be defined to create only one Constraint Set per domain or multiple Constraint Sets per domain by specifying different Rule Set names in the header using the Rule column (Rule=).

Articles in this issue

• Cover
• Purpose
• Audience
• Terms
• Overview
• Benefits of ACC
• Functional Overview
• Table and Specification Format Overview
• Mapping Name Table
• Object Table
• Rule Specification Table (Rule Sets)
• Object Rule Table (Object Rules)
• Object Rule Table (Class-to-Class Rules)
• User Interface and Data Query
• Validation and Apply Constraints to Design
• Reporting
• ACC Lab Exercises
• License Requirements / Workshop Structure
• Lab 1-1: Rule Specifications Structure Review
• Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1)
• Lab 1-3: DSP (RefDes U2) To HS Connector (RefDes U4)
• Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2)
• Lab 1-5: VIRTEX-7 (RefDes U1) To PCIe HSIO (RefDes J3)
• Lab 1-6: Viper (RefDes U34) To PCIe CONN (RefDes J1)
• Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional
• Lab 1-8: Viper (RefDes U34) To SATA Connectors (RefDes J2,J7-9,J11,J12)
• Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1)
• Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35)
• Support
• Feedback

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