When digital signals are running too fast, they can excite resonances on short traces or they can create EMI that must be suppressed. There are many methods for doing this, but with some buses, it is tempting to see an underdamped oscillation and attempt to apply damping to reduce the strength of the transient response.
Is this the right approach? It is often said that the signal swing on a digital signal creates these types of signal/power integrity problems, so it would seem that slowing down a driver component’s output would be the solution. But when is it appropriate to use series termination on an I/O to stop ringing? The answer depends on the source of ringing, and the electrical characteristics of the trace and load.
Ringing in a Transient Response
When ringing is present on the output from a digital I/O, it will appear as an underdamped oscillation on an oscilloscope measurement. The behavior is well-known as a resonant phenomenon, specifically due to excitation of the system with a stepped input. In CMOS logic circuits, this stepped input is a fast-changing digital signal that triggers a CMOS buffer circuit, and this causes a signal to propagate to the output to complete a circuit in the PCB.
When we refer to “ringing”, we’re not talking about the stair-step response you would see due to repeated reflections from an impedance-mismatched load at the end of a transmission line. Instead, we’re referring to observation of ringing exactly at the driver component’s output pin. In the case where the edge rate is fast, there are two possible causes of this underdamped oscillation:
- Resonance on short mismatched transmission lines
- Ground bounce or supply bounce on short or long transmission lines
Both effects could combine to produce a transient response short transmission lines. When this is measured in the time domain, the resulting oscillation would look like the graph shown below.
Transient responses could have multiple contributors that combine to produce ringing, or that could operate independently and combine to produce more complex ringing.
So how do we solve this problem? This requires looking at both effects in much more detail.
Resonance on Short Mismatched Transmission Lines
When a transmission line is electrically short (rise time >> propagation delay), it is possible for the load capacitance to interact with the line capacitance, line inductance, and source resistance. In these specifications, the load capacitance will help to determine the observed signal rise time on the bus. This is because the signal effectively exists everywhere on the bus, and we have three lumped circuit elements that determine the possibility of resonance:
- Trace inductance (on the order of ~5 nH/inch)
- Trace capacitance (usually ~100 pF/inch)
- Trace resistance (usually ~50 mOhm/inch)
- Load capacitance (anywhere from ~1 pF to ~100 pF)
- Source impedance (usually resistive at ~1 Ohm or less)
In this configuration, we have an RLC circuit, and it will therefore have a typical RLC transient response. The resistance in this setting applies damping, thus it is reasonable to expect that placing a resistor on the driver output will reduce the ringing. If you look at this in terms of bus capacitance and ignore the inductance, the resistor would increase the RC time constant of the bus. From both perspectives, the explanation makes sense.
However, if you calculate the limit for the critically damped case (left as an exercise for the reader), you will see that the transient response will be very weakly damped when the load capacitance is in some range, maybe 10 pF to 50 pF. This causes the damped oscillation frequency to sit below the bandwidth cutoff for the signal.
The specific limit depends on the other lumped parameter values listed above, but in general a smaller load capacitance leads to larger ringing on shorter lines. In a practical situation, this is mostly observed when interfacing with an advanced component that has low load capacitance and there is too much inductance on the line. You might observe this when connecting a slow signal from an ASIC to, for example, an I/O on a processor or FPGA as these pins will have low load capacitance.
Ground Bounce or Supply Bounce on Short or Long Transmission Lines
Ground bounce can occur on short or long transmission lines due to excess inductance in the driver component’s ground return path, and it becomes prominent during switching in CMOS buffers. The typical equivalent circuit illustrating the location of the excess inductance is shown below.
Ground bounce equivalent circuit and inductance location.
Here we also have formation of an equivalent RLC circuit between the line capacitance, line inductance, CMOS buffer parasitics (including ON state resistance), and the GND pin mounting inductance. If the line is short, the load capacitance also contributes as described above. The result is a transient response typical of an RLC circuit.
Should a resistor be used here? It depends on the electrical line length and the requirement of an impedance specification:
- If the line is electrically short and the I/O is not impedance-controlled, then a series resistor is appropriate.
- If the line is electrically long and impedance controlled, then a series resistor must not be used. Instead, place bypass/decoupling capacitors correctly and ensure you have low overall PDN impedance.
The table below summarizes the cases above and provides some guidance on solutions.
Short mismatched transmission line
Long transmission line
In a practical PCB layout, the use of a series resistor to slow down a digital signal should be limited to certain situations, specifically involving electrically short lines that are lightly capacitively loaded. The other instance is in a moderately long line on a slower single-ended bus (SPI) that has low bus capacitance; the series resistor will increase the bus’ time constant. In both cases, the resistor will slow down the signal by applying damping.
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