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Quad-SPI Brings Fast Parallel Data Transmission

Quad SPI

The serial peripheral interface (SPI) standard is one of the most successful chip-to-chip standards that has ever been used for parallel bidirectional communications. The standard persists to this data as a moderate data rate standard for extracting/feeding data to components, and it is even used in some of the most advanced components. From data extraction to configuration, there is plenty an SPI bus can accomplish. The bus is also very simple to implement in a PCB, including in boards that have multiple peripherals on the same bus.

Although the SPI bus has been very successful, it has variations that allow more complex implementation in a PCB. One of the larger SPI-based buses that is seen in some advanced systems, including high-density systems, is the quad-SPI bus. This bus is a variation on SPI and follows many of the same implementation rules used in a standard SPI bus. This article will give a brief overview of how to implement the bus in a circuit board, including buses with multiple peripherals.

What Is Quad SPI?

The quad-SPI bus is an extension of the standard SPI bus with four I/Os operating bidirectionally. The original SPI bus was developed to replace slower parallel buses with a faster single-ended, bidirectional interface. The quad-SPI bus essentially makes the standard SPI bus parallel again by adding additional I/Os.

The implementation of a quad-SPI bus is very similar to the standard SPI bus. There is one or more optional chip-select pins (CS) that can be used to toggle peripheral interfaces ON and OFF. There is also a source-synchronous clock that controls timing on the bus, and the bus has setup-and-hold times that must be obeyed. Finally, the bus is also push-pull, so it can have fast edge rates and moderately fast data rates for communication between chips. An example implementation with pin names is shown below.


Quad-SPI bus topology with pin names.

Note that there is another standard abbreviated QSPI, known as queued-SPI. These two interfaces are different. The queued-SPI standard is often used for communicating with Flash memories. It can get even more confusing because some processors will allow a single QSPI interface to operate in either quad or queued mode! Make sure to read your component datasheets to determine the mode in which the interface can operate.

Quad-SPI on a PCB

On a PCB, the implementation of quad-SPI is basically the same as with standard SPI, but with two extra traces. Follow the same setup-and-hold time, clock routing, and series termination guidelines. The last point is important because quad-SPI interfaces are not impedance controlled, and the rise time will depend on the total bus capacitance. To reduce EMI and crosstalk on edge transitions, small series resistors (about 22 Ohms) on the driver side can be used to slow down edge transitions.

Some of the other basic guidelines to follow for implementing quad-SPI in a PCB include:

  • Only route the signals over ground
  • If signal transitions are needed, use a stitching via and ground pour as needed
  • Make clock traces slightly wider to reduce their inductance
  • Use sufficiently large spacing between quad-SPI lines and other traces to reduce crosstalk

Who Is Using Quad-SPI?

Currently, there is a limited number of devices using the quad-SPI bus for parallel data transfer over multiple I/O pins. Some ASICs are on the market that include the bus built into the die. However, it is less common in processors as many of the processor options on the market are still being built on older silicon, and the implementation of these buses is not an economically strong driver to update older chip designs with a quad-SPI bus. However, there is firmware support in some MCUs that allows two additional I/Os to be used as part of a quad-SPI bus, but it may operate at lower data rates.

Although the bus is not being added to older processors, it can be easily instantiated in an FPGA. Just as is the case for many other interfaces, FPGA vendors offer IP that can be used to build an FPGA core that includes the quad-SPI interface. Some newer reference designs are taking this approach, and it remains to be seen if more conventional processors will begin to implement the quad-SPI bus as a standard feature.

When you need to place components and route your quad-SPI bus in a PCB, make sure you use the complete set of design tools in OrCAD from Cadence to build your circuit board. OrCAD includes the industry’s best PCB design and analysis software, complete with a set of schematic capture features, mixed-signal simulations in PSpice, and powerful CAD features, and much more.

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