Why SI and PI Must Be Solved Together During PCB Layout

You fix a signal integrity problem by re-routing a trace to avoid a reference plane split . The re-route crosses a power plane with high current density. Now the signal picks up power supply noise. You fixed signal integrity (SI), but broke power integrity (PI) coupling.

These problems share the same geometry. They should be solved in the same workflow. Otherwise, the PCB design cycle turns into repeated rework between signal and power domains.

Shared Structures

Figure 1. Signal and power integrity share the same physical structures. The reference plane supports signal return current while simultaneously serving as part of the power delivery network, making SI and PI inseparable at the layout level.

A ground plane is the return path for signal current. It is also the low-impedance connection for decoupling capacitors that feed the power rail. One piece of copper, two roles.

A via carries signal current when the signal changes layers. The same via family carries power current when the supply changes layers. The via parasitics that matter for signal integrity , the pad capacitance and barrel inductance, are the same parasitics that matter for PDN impedance at high frequencies.

The dielectric between layers sets signal loss. It also sets the plane pair capacitance between power and ground. Material choice affects both .

Removing copper from a reference plane, whether through plane splits, via antipads, or routing clearances, degrades both the signal return path and the PDN impedance simultaneously.

How PDN Noise Gets into Signals

Figure 2. PDN impedance peaks create voltage ripple on the power plane. Signals referencing this plane experience that ripple as noise, linking power integrity directly to signal quality.  

If the PDN impedance is too high at a particular frequency, the power plane voltage rings at that frequency during load transients. That ripple appears on any signal that uses the noisy power plane as a reference. The signal flags the power noise as additional jitter, additional amplitude variation, and sometimes timing uncertainty at the receiver.

A signal routed over a noisy power plane, even one with a perfectly clean signal return, picks up the noise from the plane it sits over. A signal routed over a noisy reference plane experiences reference voltage modulation. Because the receiver interprets the signal relative to that reference, plane noise appears as timing uncertainty, jitter, or amplitude noise. Even if the return current follows an ideal path directly beneath the trace, noise on the reference plane can still modulate the signal reference voltage. This is why PI analysis tells you something about SI risk. The cleaner the power plane, the less noise couples into the signal above it.

The reverse is also true. A signal with poor return path, bouncing return current off plane edges, injects noise onto the plane. A discontinuous return path forces return current to spread through the plane structure, increasing loop inductance and exciting cavity resonances that contribute to PDN noise and EMI. That noise becomes part of the PDN noise budget for every other signal that uses the same plane.

The Practical Consequences

Solving SI and PI separately means fixing one domain without understanding the impact on the other, this leads to common tradeoffs:

• A re-route to improve return path quality often crosses a different plane, which changes the PI coupling.

• A change in stackup spacing to improve PDN plane capacitance changes trace impedance for every signal in the stackup.

• An added set of stitching vias to suppress plane resonance also changes the return path options for nearby signals.

None of these changes are wrong. Each may be the right fix in isolation. But none of them should be made without checking what they do to the other discipline as it often creates unintended side effects.

What an Integrated Workflow Looks Like

Sigrity X Aurora reads the same Allegro X PCB Layout database that the router uses. There is no export step. There is no separate geometry model to keep in sync.

Figure 3. Signal and power integrity analyses operate directly on the same PCB layout database. Because both workflows use identical geometry, there is no need to export or maintain separate models, enabling rapid iteration between layout changes and electrical verification.

From that shared database, you can run signal integrity analysis on your high-speed nets, check PDN impedance on your power rails, and look at how the two interact. When a PI analysis shows a resonance peak at a given frequency, you can ask whether any signal references the resonant plane. When an SI analysis shows a problem at a via transition, you can ask whether the return stitching is also providing PDN support.

The value is in the loop: find the problem, understand the physics, make the change, verify that both SI and PI stayed healthy. The loop stays tight because the entire workflow shares a common database.

The Electrical Link

Power integrity and signal integrity are not separate disciplines that happen to live on the same board. They are two measurements of the same electromagnetic behavior. One measures the voltage delivered to the IC pins. The other measures the voltage delivered to the IC receiver inputs. Both measurements depend on the same copper, the same vias, the same dielectric.

The fields do not separate just because the analysis does.

Fix them together. The board will come back cleaner, the lab debug cycle shortens, and design iterations converge faster because the same physical system is being validated as a whole.