IPC-7351 is the primary standard concerning land pattern creation for surface mount components. When people think of footprint creation for modern components (SMDs), they probably look for a footprint generator with land patterns matching this standard. A professional footprint needs more information than what you’ll find in the land pattern, including silkscreen and a courtyard layer, which might be placed in layer pairs hybrid components.
If you have an SMD component and you need to define a component outline, should you use the silkscreen layer, courtyard layer, or both? In some cases, these two outlines might overlap in the footprint, but is this acceptable? We’ll break down how to use these layers in this article.
Where’s the Courtyard?
Courtyards are a layer used only in the PCB design tool to identify clearance zones around a component in a PCB layout. Basically, they can be thought of as a keepout, but your design tool will not trigger DRC errors if these regions are violated.
Courtyard outlines are visualized in this example. These outlines are used to define placement limits between neighboring components.
The intention in defining courtyards is to set a minimum clearance level around a component. Therefore, the courtyard outlines around two different components can overlap. If you also want to visually define a courtyard in the silkscreen, you can copy the courtyard outline to the silkscreen layer.
If you do copy the courtyard outline to the silkscreen layer, this can be useful. Many designers will place parts with the silkscreen visible, so it allows the courtyard limits to be seen in the same view. This is important for designers, but not so important for manufacturers; a manufacturer only needs to verify that DFM/DFA rules are not violated with regard to silkscreen placement.
Do Manufacturers Need Courtyard Data?
No, manufacturers do not need courtyard data. Courtyards are a tool for designers and they are not something a manufacturer really needs to know about. If you send a complete data package with Gerbers and ODB++ files, you have the option to export a courtyard layer pair (top and bottom), which can then be viewed by an assembly house. You could also send an IPC-2581 export for your design, which will also include this information for review by the manufacturer.
Despite all the effort that gets put into creating courtyard outlines in PCB footprints, many designers do not use them. Instead, they favor aggressive placement tactics that align with high-density placement. Doing this correctly requires correctly setting design rules so that components are not too close together.
Use Clearance Rules When Ignoring Silkscreen and Courtyards
If the silkscreen and courtyard are placed together so that they touch each other, and you are designing a dense board, then the silkscreens will also touch each other. Two silkscreen lines that make up component outlines for different parts touching each other represent the absolute limit of placement as defined by the PCB footprint designer. Remember, the footprint designer is the one who determines the courtyard and clearances required for a particular footprint, not the PCB layout engineer.
However, the PCB layout engineer does not need to fear as they still have tools they can use to set clearances in the event courtyards are overlapping each other. This would be done in the PCB design rules with the following entries:
- Part-to-part clearance
- Pad-to-pad clearance
- Minimum solder mask sliver size
- Minimum silkscreen clearance
- Silkscreen-to-solder mask edge clearance
If you opt to ignore limits defined in the silkscreen and/or overlapping courtyards, then the most important is the solder mask sliver size and the silkscreen-to-solder mask edge clearance.
First, the silkscreen-to-solder mask clearance applies where the silkscreen is coming very close to the edge of the solder mask, and it is a proxy for checking whether silkscreen is overlapping with a component pad. If the silkscreen and exposed copper do overlap, then you need to move the silkscreen (if it’s a reference designator) or delete the silkscreen (if it’s an outline).
This silkscreen is getting very close to the edge of a copper pad. Excessive misregistration or a large positive solder mask expansion opening may result in silkscreen being applied to copper or to bare laminate.
Second, the solder mask sliver is a proxy for the clearance between two copper pads. When two pads edges are too close together (less than about 5 mils), the leftover solder mask might flake away from between the pads. This can sometimes be solved with negative mask expansion, but you will still be limited by the pad-to-pad clearance requirement between SMD pads. Given a 5 mil limit, and 1-2 mil positive solder mask expansion, this is equivalent to an 8-10 mil pad-to-pad clearance requirement for SMD components.
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