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Anywhere but here – Getting the Traces Away from the core


Somewhere along the way, electronics changed. Of course, technology is continuously evolving with incremental improvements. Once in a while, there is a game-changer advancement that opens new opportunities for everything. The day we pulled the pins from the perimeter to the underside of the package was one such day. A surface mount was one thing, ball grid arrays (BGAs) were the “killer app” that leveraged all of the miniaturization that was surrounding the quad-flat-pack designs of the past. For those QFPs, the gull-wing leads could be spaced no better than 0.5 mm pitch around the edges. (We’re below that now.) That lead pitch limited the number of pins you could reasonably have on a device. The geometric advantage of filling in rows of columns of connections was a leap forward from the edges.

It also left part of the chip team’s work undone. The ball-out has replaced the fan-out at the component level. A die is attached to a substrate, and a via takes that signal to the other side of the substrate where the solder ball is applied. Chip Scale Packaging can be brutal for getting all of the nets in and out. Fortunately, most electronic devices still come in larger form factors. If you can stay above 0.8 mm pitch BGAs, then you can probably find a standard PCB construction method that would fit your requirements. Way back in 2016, I heard the EE admit that it was a mistake to try to use only QFN devices for a project because they were getting harder to source.


We’ve taken the plunge into an 800 pin SOC! Ok, the example I’m using is not that bad but still, we’re faced with the dizzying amount of connections to route out; we need some strategy. Here is what I would do first. Ground. One for one, every ground pin gets a via. That could be 10% or more of the connections right there. It would be all that remains of the big ground slug in the middle of the traditional packages. We get the same physics regarding junction temperatures no matter the packaging. More than likely, you would start with all of the pins connected to a via in some way. The point becomes to preserve those ground vias and only gang two together to perform the miracle of creating space where there was none before. The ball map is not going to yield all of its secrets on the first try.

I would caution against incorporating the fan-out vias at the symbol level. It will trap you into a technology. I can testify that strange things are liable to happen when you update a device generated with a built-in via type. All the no-connect pins suddenly had a via. Cleaning up that mess was a riot.

Use your copy skills or semi-automation to create the short trace and the via adjacent to each pad except for those on the outer row or rows and, of course, the no-connect pins. The outer row has to fend for itself, routing away on the outer layer. If the row inside that one can also escape on the outer layer, figure those in as well when allocating the precious real estate around the device. The goal, in this case, is a lower layer count by spreading the density out. Route away on the top as much as possible.  If the PCB has no real estate that isn’t already covered on both sides with components, then throw that advice out and get on with your HDI mastery.

Filling in the power domains

BGA technology often ends up being double-sided so the decoupling caps can nest between power and ground pins. Small caps make sense and become necessary as the pin-to-pin pitch decreases. Some devices almost beg for diagonal placement of the caps. Good fundamental bones of a PCB layout start with taking care of the power. That goes double for mobile products. Your power integrity engineer will appreciate it if you can locate the strongest power plane high up in stack-up so that it is physically close to the device. Above the centerline of the stack-up would be nice.


Image credit: Author. Note the other circuits leaning away from the diff-pairs in this bottom view.

The way most stack-ups work, some layers make better routing layers than others. If I have a processor on the top of a 12-layer board that uses through-hole technology, layer 3 is going to leave us with a 9 layer via stub in the Z-axis. If the board is not back-drilled, that could be a rough way to go for your most needy circuits. So we’re taking these little differences into account when we do our high speed and/or RF routing first. Save that not-so-great layer for future improvement. It will be the one between a solid ground plane and a split-up power plane. Use it for those short runs that don’t cross over any gaps. During the Obama years, this technique got the name “bail-out layer” and it stuck. If you get the whole thing routed and barely touched the bail-out layer, you are ready for REV 2.


You should bake all of the linewidths and air gaps for proper impedance into the design. They may be impossible to achieve in the confines of the device footprint. We explain that part about doing the job of the substrate at the PCB level and use a zone constraint where the rules are basically a compromise of whatever works and apply on whatever layers are necessary. If I can help it, I don’t neck down traces just because they enter the special rules area. That is the impetus for creating zones by layer rather than for all layers. Ideally, the only geometry that would change is the copper pour to via rule so that the pour can get between the pin field.



Image credit: Author - note the via size and air-gaps shrink automatically within the perimeter of the device.

Differential pairs can be a nuisance since they want to stay side by side. Creating a channel for them might be accomplished by moving rows or partial rows of vias from one quadrant to another. Picturing the typical view of a BGA fanout, all of the vias radiate out from the center. The vias in the upper left all route out to the top left and so on.  Turning off the pad layer shows a cross-shaped aisle way between the four separate grids of vias. These wider spaces from the vias going in different directions do not always have to be right down the middle of the design. You could “part the hair” on a row that needs a fat shape or a big air-gap. Don’t let symmetry get in the way of your pin escape plan.

routes and traces


Image credit: Author. Note the various directions for via launch in this top-down view.

There are going to be exceptions, but it is rarely a good idea to route clear through the pin field. It would cut off channels that are going to be needed, especially if the PC board has a low layer-count as part of the design parameters. 90% of the time, the vias are spaced such that one trace can be routed between them. Two tracks between vias is a luxury that tells me that we’re using a device that might not be on the market much longer. The trend, however, is towards narrow lines taking up fewer layers. The pressure is on line width, air gap and via size to share the vanishing space.


Image credit: Author. Using all channels for inner-layer escape and adding a guard band around the noise maker.

Following power, ground, high speed, and controlled impedance are the sensors and the noisemakers. Keep these two apart. Count on the crystal to be a bad neighbor. Use short, protected routing to contain the EMI fields. The sensors are really fussy. Only circuitry directly related to the sensor should be anywhere near it. That applies to all of the layers near these electronic wonders.

The rest of the story

Various busses need to be gang routed as a river; usually on a single layer from start to finish. Clocks are the same as the crystal, they’re aggressive and need extra isolation. Eventually, we get down to the 20% of the nets that are not a problem and have no special rules on them. That doesn’t mean that they will be easy. Their goal is to escape without breaking any of the good work done before.

You do not need a complete netlist to do a fan-out study. You can start pulling signals out of a chip using thinner lines or additional layers until you can gauge the type of geometry needed to break out of the pin field. I generally start on the outer rows and work inward to come up with a baseline stack-up to present to the PCB fabrication shop for sanity checking. By this means, the study can be completed well before any actual placement or routing takes place. The more you know going into the actual layout, the more efficient and confident you will be when it is time to shine.




About the Author

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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