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How to Avoid Metastability in Digital Circuits

Key Takeaways

  • Metastability is inherent in any system handling bistable states of 1 and 0 or high and low. 

  • The primary reason for metastability in digital circuits is the set-up and hold timing violations. 

  • Clocking multi-stage synchronizers by using the output of a clock doubler is one proven method to avoid metastability. 

Flip Flop Flip-flops are fundamental blocks of digital electronics

Flip-flops are fundamental blocks of digital electronics; they are used in applications involving latches, counters, registers, memory, data transfer, and data storage. They operate with two stable states–either 0 or 1. Whenever there are timing violations, flip-flops enter into a quasi-stable or metastable state. Metastability conditions in flip-flops are detrimental to their output and they often show oscillatory behavior.

There are several solutions for how to avoid metastability in flip-flop applications. The appropriate way to avoid metastability changes with the platform and application. We will discuss metastability and its preventive methods in this article. 

What Is Metastability in Digital Circuits? 

In digital circuits, we deal with asynchronous and synchronous systems. When interfacing an asynchronous input signal to a synchronous system, or whenever a signal is shared by two asynchronous clock domains, the possibility of the system encountering metastability is high. Most often the metastability occurs in flip-flops when the input signals violate the timing requirements.

In any design, flip-flops have a specified set-up time and hold time. The minimum time before the clocking activity by which the input signal must be stable is called set-up time. The minimum time after the clocking activity, during which the input signal must remain stable, is called hold time. During the set-up and hold time, the input signal is not legally permitted to change its state before and after the clocking event. When the input signal transitions violate the set-up and hold times of the flip-flop or change state during the set-up or hold time, the output enters an unknown or unpredictable state called the metastable state. Metastability is the propagation of the metastable state.

Metastability is inherent in any system handling bistable states of 1 and 0 or high and low. The output becomes incapable of reaching the confirmed state of either 1 or 0 within a specified period of time. Metastability conditions make it difficult to predict the digital circuit output level and the time required to return to a stable state. The time duration is dependent on the ambient conditions as well as the process technology used to manufacture the device. 

Causes of Metastability in Digital Circuits

The primary reason for metastability in digital circuits is set-up and hold timing violations. There are several conditions in digital circuits that lead to timing violations and, therefore, metastability. Interfacing asynchronous signals to a synchronous system is common in digital circuits and it is the most common condition leading to the metastable state in digital circuits. Some other causes are:

  • Signals traveling to a digital sub-circuit in an overall system with two different and unrelated clock signals. 

  • When the rise and fall time of the clock signals is greater than the tolerable values, it increases the skew or slew of the clock. The high slew rate of the clock signal increases the time required to enter the stable state in digital circuits. 

  • The interfacing of two domains operating at different frequencies or the same frequency with different phases.

  • In ceratin flip-flops, the combination delay is such that the data change sits state in the critical window, which is the sum of the set-up and hold window. The larger the window, the higher the chance of metastability in a digital circuit.

Avoiding Metastability in Digital Circuits

So, how do you avoid metastability and why is it so important? The condition of metastability in digital circuits propagates errors to the remaining part of the circuit. Metastable states give intermediate values other than high or low or 1 or 0, leading to logical incorrectness. The output can get glitchy, oscillate, or be invalid under metastability, causing excessive propagation delays and system failures. The time duration to which metastable states remains is unbounded, and this intensifies the effects of metastability in a circuit. It is very important to avoid metastability to get rid of logical misjudgments resulting from it. Some of the methods to avoid metastability are:

  1. Synchronize the asynchronous input signals with the system clock before applying them to the synchronous system.

  2. Design the digital circuits, especially flip-flops, registers, and FPGAs, with a long clock period that allows for the resolution of the metastable states and for the delay of the signal that may be in the path of the next flip-flop. 

  3. Add multiple synchronizing flip - flops or synchronizers to the signals that travel from one clock domain to another. It gives an entire clock period to resolve the metastability in the first synchronizing flip-flop. Using two-stage synchronizers to avoid metastability in digital circuits is called the double flop technique. However, the increased latency in the system to respond to asynchronous input is a disadvantage of this method. 

  4. Clocking multi-stage synchronizers by using the output of a clock doubler is one proven method to avoid metastability. This method improves the response time to asynchronous input compared to synchronizers without clock boost.

When you think about how to avoid metastability in digital circuits, correlate it with the mean time between failures (MTBF). Increasing the MTBF reduces the chances of metastability in systems. It is possible to improve MTBF in a digital electronics circuit by modifying the design or by using the right methodologies. You can use Cadence’s PCB design and analysis software to design bistable digital circuits free of metastability.

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