Using Net Classifications to Optimize Your PCB Layout
The problems and challenges of not having nets organized by classes for routing.
How PCB net classifications can help with net organization.
Using PCB design tools to set up net classifications to manage net rules and constraints.
Trace routing on a printed circuit board
For a long time now, the shop area in my garage has been a mess. Not only is it filled with unfinished projects, tools, and spare parts, but it has also become the de facto dumping ground for everything else that doesn’t have a regular spot in our house. With it being such a mess, I can no longer use the shop as I want because I can’t find the tools and parts that I need for my projects. I have to dig through the pile to find a hammer and then dig again to uncover a box of nails.
The frustration that I have with my cluttered shop reminds me of the problems I used to have when routing PCB designs. Without proper net organization, it takes a lot of effort on the part of the designer to remember and incorporate all of the various trace routing requirements. I would have to check each sensitive net when I was done to make sure I hadn’t violated its unique spacing rules and trace widths. While this wasn’t as big of a problem on smaller boards, it was a painful experience on my larger boards that had higher net-counts.
Thankfully, I started assigning rules and constraints to my nets to organize my routing, which took a lot of the pressure off of me. Now my nets carry the specific trace width and spacing rules for their function, which are automatically applied so that I don’t have to rely on my ability to remember each detail. If this sounds like it would be helpful to you, take a look here at how PCB layout net classifications can be used to optimize your layouts as well.
The Design Challenges of Not Organizing Printed Circuit Board Routing
When designing a smaller printed circuit board, net organization isn’t as big of a problem as it is with larger boards. With 100 nets or less, you can usually keep track of the important signals. And, power and ground are usually easy to pick out of the crowd.
But on larger designs, it can begin to get a little more confusing. You may be dealing with multiple power and ground nets with different connectivity requirements in different areas of the board. There also may be data and address buses that would benefit from being separated to help identify them for specific routing patterns. With boards that have thousands and thousands of nets in them, it is usually impossible to keep track of all the various net details without the help of tools.
High-speed designs complicate the matter even further. In addition to multiple power and ground nets, as well as the data and address buses, you will also need to contend with:
Controlled impedance lines.
Clocks and other sensitive signals.
Groups of nets that may require routing at specific lengths.
Nets that have specific routing topology requirements.
Differential pair routing.
All of these high-speed nets may also have different trace width and spacing requirements. On top of that, they may have specific layer assignments or restrictions and individual length and matched length requirements. In the case of differential pairs, they will also have to be routed together and match each other perfectly while still maintaining their specific widths, spacing, and spacing to other nets.
You may also run into dense areas of the board where the traces will have to be reduced in width to complete their routing. This type of routing is also known as necking down, and it is often necessary under high-pin count devices, like ball grid arrays (BGAs), where their routing patterns are extremely tight.
Without the help of tools, in cases like these, the designer must manually change the width of the trace to get the traces connected. Trace necking requires working with new routing grids to get the tracing in as well as redefining the trace spacing requirements. Routing traces out of a BGA with hundreds and hundreds of pins on it can result in a lot of intense manual work for the designer.
Fortunately, there is a way PCB design tools can help the designer to organize their work and optimize the routing of traces.
Trace routing rendered in 3D on a PCB Design CAD system
How Can Using PCB Layout Net Classifications Help?
In today’s PCB design CAD systems, you can assign trace routing requirements to the individual nets in your design by using design rules and constraints. This will give you control over the trace width, spacing, length, and topology values for each net, and the tools will check these values for you through online design rule checking.
This will ensure your traces will meet the routing requirements you need. The catch, though, is that for a board with thousands of nets, it could result in a lot of work to set all of this up. Here is where setting up net classifications can be really helpful.
A net classification, or net class, will allow you to group like nets together and assign a rule set to them. For instance, you would start by assigning the default rules to all nets, and then you would create a class just for your power and ground nets. Once classified, you can assign a specific set of rules and constraints for power and ground. If you have multiple power and ground nets with different routing requirements, you simply assign them to additional net classes that are linked to a different set of rules and constraints.
After that, you would create even more net classes for the address and data lines as well as the other high-speed routing requirements mentioned above. As with the power and ground, you would assign unique sets of rules and constraints to these classes as well.
This may seem like a lot of work, but thankfully, there are tools designed to make the job easier for you. In Cadence Allegro, the assignment of net rules and constraints to nets and net classes is done using the Constraint Manager. This tool works between both the schematic and layout side of the Allegro tools and communicates design rules and constraint changes bi-directionally.
In the picture below, you can see that by selecting a group of nets in the schematic, those nets are in turn also selected within the Constraint Manager. This allows for routing information to be attached to the net class during schematic capture, which will then be forwarded into the layout.
The Constraint Manager gives the user a lot of power and flexibility by being able to identify and group nets according to their name or by selecting them from the schematic or layout. This saves the user a considerable amount of time from having to input all of this net information manually. Next, we’ll take a look at how Cadence Allegro handles this process and how that will make your job in layout much easier.
Allegro’s Constraint Manager showing the nets that were selected in Capture
Using the Constraint Manager in Allegro to Organize Your Nets
The Constraint Manager within the Cadence Allegro tools gives the user a lot of functionality in terms of how to configure the display of its data. You can assign priorities to different columns to limit their display as well as change the width of the columns. You have many different ways to view and work with the data as well. For instance, you can work with your spacing rules by either the rule sets themselves or by the net names, net classes, regions on the board, or interior layers.
The first thing to do is to create a new rule, if one doesn’t already exist, that you can assign to a class of nets. In the Constraint Manager, there are different rules that can be created, such as physical or spatial, and their creation is a simple process. You will give the new rule a unique name and input the required values.
Once the rule is set up, the next step is to create the net class. As you can see in the picture below, we have selected a group of nets from the layout and used the Constraint Manager to create a new net class based on what we have selected. With the net class created, the next step is to assign the rule to it and then you are done.
With the ability to create different rules and constraints in Cadence Allegro, you can control exactly how each net or classification of nets will be routed. You can set rules for:
Trace widths, including necking down sizes.
Spacing between traces as well as unique spacing to specific nets.
Spacing to specific design objects such as thru-hole pins or SMT pins.
What layers specific nets can be routed on.
Specific trace widths or spacings in certain regions.
What vias will be used for individual nets or net classes.
What the trace width and spacing will be for differential pairs.
From there, you can also set up rules and constraints that can be assigned to net classes for trace lengths, routing topologies, signal integrity, timing, and impedance.
Creating a net class from some selected nets in Allegro’s PCB Designer and Constraint Manager
The Constraint Manager used in Allegro is a powerful tool that allows you to set up all the rules and constraints that we have been discussing, but it goes much further. You will also find rules and constraints that can be set up for manufacturing as well to control the placement of components, silkscreen, and solder mask. Allegro gives you a lot of versatility in designing your board. For more information on routing, take a look at this E-book.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.