Thermomechanical Analysis for Your Thermally Cycled PCB Designs

Key Takeaways:

• Learn about thermomechanical analysis as a process to augment electronic design
• Discover how thermomechanics are involved in conductors and vias
• Understand new potential uses to augment via and conductor placement

This lava lamp works by thermal expansion and contraction as the temperature of wax changes.

Heat is always a consideration in products with plenty of computational power, and you’ll need to remove heat to keep components at a safe temperature. Another aspect of thermal management is examining thermal expansion at high temperature, which places stress on critical structures in a PCB, especially in the HDI regime. Examples include fine-pitch BGAs and high aspect ratio microvias.

More boards are being pushed into the HDI regime, and other boards can experience a large temperature rise during operation. Simply reaching a high temperature is not always a problem, the more dangerous problem that can lead to failure is repeated cycling. If you have access to a powerful 3D field solver for thermal CFD simulations, you can identify which structures in your board will reach unacceptable temperatures and experience stress from thermal expansion.

A Thermomechanical Analysis Process for PCBs

Since thermal expansion is so important in any PCB that will be repeatedly thermally cycled, you’ll need to determine by how much conductors in your board will expand during cycling. As a board is brought to a high temperature, the substrate and conductors expand, but they can expand at different rates. FR4 substrates experience greater expansion than copper, which puts stress on conductors. Traces on a board are less susceptible to failure as they are sufficiently thick. The real reliability danger lies in brittle solder joints and vias, particularly microvias and un-backdrilled plated through-hole vias.

In FR4, the thermal expansion coefficient (CTE) increases once the board’s temperature rises above the glass transition temperature. It is always best to use a high-Tg laminate if your board will run at a high temperature as you want to stay below the glass transition temperature. As everything in your board expands, stress accumulates and causes microscopic cracks to propagate in the conductors. After repeated cycling between high and low temperatures, these cracks can merge, which leads to fracture. More ductile materials (i.e., solder with added indium) can experience more cycles before failure. This relationship between heating and thermal expansion is central in thermomechanical analysis.

Simulating microcrack accumulation during repeated thermal cycling is not a simple problem, and simulating this directly is a complex random-walk problem in a random system. However, if you have experimental data on microvia reliability and solder joint reliability due to thermal cycling, you can accurately estimate the number of cycles you would expect to cause fracture. In general, when the difference between the extreme temperatures is smaller, the board can withstand more cycles.

The thermomechanical analysis process for electronics proceeds in the following order:

1. Steady-state temperature calculation: Calculate the steady-state temperature while a board is in operation. This should include the operation of all cooling fans and components.

2. Convert temperature rise to volume expansion: Once the temperature in each region of a board is calculated, it can be converted to a volume change using a CTE value.

3. Calculate strain on various structures due to expansion: The strain experienced by different structures in the board is equal to the volume expansion. For a via, which gets mechanically stressed under expansion, the via experiences some additional mechanical strain.

The best tool for calculating the steady-state temperature distribution is to use a thermal CFD simulator that builds an FEA/FDTD mesh directly from your design data. The temperature change you calculate in the system is then multiplied by the CTE value, which determines the thermal strain. To the total strain on conductors, you need to consider the exact structure being strained during expansion.

Conductor and Via Reliability in Thermomechanical Analysis

Conductors on the surface layer or internal layers are less susceptible to thermal failure under repeated thermal cycling. Instead, vias are susceptible to fracture at specific locations. The root cause of thermomechanical stress on vias and fracture is the mismatch between the CTE values of copper conductors and the substrate material. 

Copper has a CTE value of ~16 ppm/K, while FR4 has a CTE value of ~70 ppm/K along the thickness direction. The image below shows how the expanding substrate places stress on via structures. The yellow arrows show the location and direction stress is applied to vias.

Comparison of thermal stress on vias in thermomechanical analysis. The yellow arrows show the locations and direction of stress due to substrate expansion.

Here’s how different via structures are susceptible to failure during thermal expansion. Note that the lands, pads, and barrels in a via can experience fracture, but there are specific locations that are known to be highly susceptible to fracture.

High and Low Aspect Ratio Plated Through-hole Vias

Through-hole vias with high aspect ratio are most susceptible to fracture near the middle of the via barrel. This occurs because plating solutions are drawn into a via hole through capillary forces, and the plating solution can deplete from the via barrel near the center when the aspect ratio is large. This means the resulting plating is thinner near the center of the via barrel. Lower aspect ratio through-hole vias can be more uniformly plated, meaning the plating thickness near the center of the via barrel is comparable to that near the ends of the via. Assuming your stackup is symmetric, then one would expect fracture to occur slightly closer to the top surface layer.

Microvias

The neck and base of microvias are most susceptible to fracture after repeated thermal cycling or when the board experiences extreme expansion. The neck region curves inward and stress can concentrate in the microvia transition region. At the base, laminate layers pull on the interface between blind/buried vias, again creating a risk of fracture. Some microscope images showing microvia fracture at the base of two microvias are shown below.

Crack at the base of a copper-filled microvia. Image source: IPC.org

Once you’ve identified susceptible structures in your board, you can pinpoint which areas are candidates for more aggressive thermal management solutions. Some simple choices like using a different substrate or rearranging components can bring temperatures low enough that the board can withstand repeated thermal cycles without failure.

Whether you’re evaluating via reliability or your overall thermal management strategy, you need the right PCB design and analysis software that integrates with a multiphysics 3D field solver for thermomechanical analysis. Allegro PCB Designer and the Celsius Thermal Solver from Cadence provide a powerful set of solutions for PCB layout and thermal management alongside Cadence’s full suite of analysis tools. You’ll have access to the design, simulation, and analysis features you need to create powerful new electronic products.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.