Thermal Cycling Resistance and PCB Failure
Thermal cycling can put stress on conductors in your PCB due to a mismatch in thermal expansion coefficients.
Failure in solder balls can occur due to lack of ductility throughout the solder ball, which causes the ball to fracture near its edges.
Thermal cycling failure in vias is most prominent in high aspect ratio vias and blind/buried vias in HDI boards.
The vias and solder joints in this board need to have high thermal cycling resistance to prevent fracture.
Every electronic device has a rated lifetime, but premature failure can still occur due to mechanical shock, thermal shock, and vibration. Thermal cycling is simply the thermal analog of vibration—repeated mechanical stress is exerted on structures in the PCB leading to fatigue and failure. After repeated thermal cycling, a later period of temperature rise and volumetric expansion can cause mechanical failure.
Thermal cycling resistance is not a specific physical property that can be measured. Instead, it’s simply a quality of an electronic device referring to its ability to withstand thermal cycling. Components have their absolute maximum temperature ratings that need to be adhered to, but repeated thermal cycling can cause failures in two PCB structures: solder and vias. Let’s look at how thermal failure arises in each of these structures and what you can do to help prevent it.
Thermal Cycling Resistance in Vias
Vias are one structure that is prone to fatigue failure and fracture under repeated thermal cycling. Although these structures are prone to fracture at extreme temperatures, preventing failure under thermal cycling is all about the mechanical design of vias. The selection of the right substrate material also aids thermal reliability. These points apply to both high aspect ratio vias and blind/buried vias in HDI boards.
Just like solder ball reliability, failure under thermal cycling occurs due to a mismatch in the CTE values for copper and the substrate. FR4 is an anisotropic material with a CTE value of ~70 ppm/°C perpendicular to the board surface; note that this is different from the CTE values along the surface, which are ~13 ppm/°C. For comparison, copper has a CTE value of ~16 ppm/°C. This means stress is primarily subjected along the axis of the via when the board heats up to a high temperature, as shown in the image below.
Forces on a through-hole via due to thermal expansion of the substrate.
The above image shows forces on a plated through-hole via, but a similar diagram could be drawn for blind or buried microvias. The effects of this stress depend on the geometry of the via, particularly on the aspect ratio and structure of the via. Locations of stress concentration also depend on the via deposition and plating method, which involves deposition from solution.
Blind and Buried Microvias
Blind microvias have slightly thinner plating near the neck of the via. This is the primary fracture point for blind vias on the surface layer where the expanding substrate pushes up against the neck of the via. Stacked blind and buried microvias are prone to fracture at the interface where they are stacked. In other words, the neck region of a buried via can separate from the bottom of the via above it, producing a high resistance connection or an open circuit.
The IPC recently issued a reliability warning to be included in the IPC 6012E standard, and reliability problems with blind and buried microvias must be assessed during fabrication. To ensure reliability during manufacturing, the standard test methods in IPC-TM-650 (Method 2.6.27) call for test coupons to be subjected to a normal solder paste reflow profile such that they reach a peak temperature of 230 °C or 260 °C while connected to a 4-wire resistance probe for six full reflow profiles. As long as the resistance does not increase by more than 5% during this repeated reflow profile, the board can be regarded to have sufficient thermal cycling resistance to be put into service.
High Aspect Ratio Vias
When a typical through-hole or buried plated via is deposited during fabrication, the plating solution undergoes capillary action. Surface tension influences how the plating solution is drawn into the via when the board is immersed in the plating solution and copper begins depositing along the via wall. If the plating solution is not sufficiently stirred and agitated during deposition, the copper precursor gets consumed faster near the center of the via barrel due to meniscus formation.
This causes the central region of a via barrel to have thinner plating than at the via neck. If the aspect ratio of the via is larger, then the copper coating in the interior of the via will be thinner. Once the substrate expands at high temperature, the center of the via will experience greater stress concentration and will be more prone to cracking.
There are three possible solutions here, which involve design and manufacturing:
Use a via with a smaller aspect ratio. For longer vias, this simply means making the via diameter larger.
Use a PCB substrate with a CTE value that is closer to that of copper. For some designs, such as high-speed designs requiring low-loss laminates, you may need to compromise other substrate material properties for a lower CTE value.
Ensure your fabricator uses a lower viscosity plating solution with sufficient agitation to deposit copper plating more evenly in the via barrel and neck.
Just like vibration fatigue can produce mechanical failure in solder balls, so can thermal cycling. When the temperature of a solder joint increases to a high level, the solder expands at a lower rate than the substrate, but the forces involved are very difficult to predict. Stress concentration in solder balls is easier to predict, and finite element method (FEM) models show that stress concentrates near the top and bottom of the ball, leading to fracture.
Any of these solder balls could crack under repeated thermal cycling.
As long as the solder joint is sufficiently strong and ductile, the joint will be able to withstand repeated thermal cycling. This means fabricators need to address any factors that can compromise solder joint strength and ductility. These include corrosion, inadequate wetting, insufficient solder, and other factors that can only be addressed by fabricators. Be sure your manufacturer understands the thermal environment in your board when preparing your design for manufacturing to prevent solder joint failure under repeated thermal cycling.
Thermal Management Is Key
Under repeated cycling, stress accumulates and dissipates creating the potential for fatigue failure in addition to stress fractures. As long as a layout is properly designed and qualified, and as long as a thermal management strategy is in place, your board will have greater thermal cycling resistance and a longer lifetime.
When you use the right PCB design and analysis software, you’ll have the design features you need to create boards that are reliable and have sufficient thermal cycling resistance. The design tools in Allegro PCB Designer from Cadence integrate with a full suite of analysis tools for post-layout simulation and board evaluation. Try this unique toolset when you need to design reliable PCBs for advanced applications.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.