This IC and these other components require stable power and decoupling
A long time ago, in an electronics lab far, far away, power integrity and signal integrity problems were something of an afterthought. Signals were switching slow enough that interference between different portions of a digital system was practically unobservable. Even after TTL logic became fast enough to require standard methods for preventing crosstalk and interference, power integrity problems, particularly power bus ringing, were still negligible as long as your power supply was sufficiently stable.
You can thank ECL for revealing power integrity problems that lead to serious signal integrity problems. Over the past 30 years, ever since ECL stopped being confined to supercomputers and made its appearance in the wider market, designers working with high speed digital systems now need to confront power integrity problems and take real steps to solve them. With newer PLDs like FPGAs, high-performance MCUs, and many ASICs and SoCs running at high speed/high frequency and with razor-thin noise margins, designers need to take greater steps to ensure high performance designs do not experience significant power fluctuations.
What is Power Bus Ringing?
Power bus ringing always occurs in your PCB; the issue you need to consider is whether or not ringing is intense enough to be observed in your board. If you’ve gone old school and are working with 12 V CMOS logic, you probably won’t have to worry about anything, even with an unregulated power supply. With modern logic that runs at 1.2 V and ICs that draw amps-worth of current, power bus ringing can be significant. Logic families that switch faster than a few ns require significant decoupling to ensure power integrity, which will be discussed in greater detail below.
When a device like an FPGA switches repeatedly, particularly when a large number of gates switch and draw current from the power supply, the sudden burst of current can produce a transient current and voltage response in your PDN. This transient response generally appears as an underdamped oscillation in the voltage level. The transient current and the transient voltage are related by the impedance of the PDN:
Relationship between power bus ringing voltage and PDN impedance
This transient voltage/current oscillation is typically called power bus ringing. This relationship between the transient voltage and transient current is the reason that the target impedance of your PDN becomes extremely important. The current drawn by the switching IC is fixed, and the resulting transient voltage needs to be reduced as much as possible to ensure power integrity. This is why we say that the impedance of your PDN needs to be below some target value. For a given transient current, a smaller PDN impedance will produce smaller power bus ringing. This will reduce the variation in voltage seen by the supply pins on a PDN.
Although power bus ringing is sometimes called power supply ripple, the two terms essentially refer to different phenomena. Ripple generally refers to the leftover oscillation in the power supply voltage and current due to AC-DC conversion, while ringing refers to a transient oscillation that arises when ICs switch state or output level. Power supply ripple appears on the output from an unregulated power supply; if you measure an oscillation on the output from a regulated power supply, then it is most likely due to ringing. Furthermore, ripple from power conversion appears at 60 Hz (in North America) or 50 Hz (in Europe), while power bus ringing will appear at much higher frequencies.
Reducing Power Bus Ringing with Decoupling
If you look at a typical circuit model for a PDN, it appears as a complicated RLC network with various RLC portions in series and parallel (see below). This model include the parasitic capacitance provided by power planes/power rails and ground planes, parasitic inductance, and resistance of the various conductors that make up your PDN.
Although decoupling capacitors have received an unfortunate name, they don’t decouple anything; their job is to provide a reservoir of charge to compensate the transient current in power bus ringing as an IC switches. In essence, the switching IC should draw charge from the decoupling capacitors rather than the power supply. This fact is one way that you can size decoupling capacitors; the total charge drawn from the decoupling capacitor should be equal to the time integral of the transient current.
When viewed from another perspective, the impedance of your PDN will be inversely proportional to the square root of the equivalent capacitance in the PDN and decoupling network. This is one reason why decoupling capacitors are added between the power and ground points; the capacitance from the decoupling capacitors and the parasitic capacitance between the ground plane and power plane/power rails are in parallel, so the combination of these elements increases the capacitance of the PDN, which decreases the impedance of the PDN, thus decreasing the magnitude of power bus ringing.
Example circuit model for describing power bus ringing
With ECL and similarly fast logic, the best way to ensure sufficient decoupling is to use power and ground planes in order to ensure sufficiently low PDN impedance as this arrangement of plane layers provides sufficiently large capacitance. This is preferable to using a large number of big decoupling capacitors throughout your PDN. Place components on the top layer, followed by a ground plane, and then the power plane.
There is another issue that needs to be considered when describing power bus ringing: the self-resonance frequency of capacitive elements in your PDN. One should note that these self-resonances are responsible for the impedance peaks and valleys seen in the impedance spectrum of a PDN. Compensating for self-resonances in a PDN with bypass and decoupling capacitors can be done by adding a small inductor (sometimes called a decoupling inductor) between the decoupling capacitor and an IC.
Power bus ringing due to transient oscillations are unavoidable, but you can design the right decoupling network and simulate its behavior when you use the right PCB design and analysis software package. The simulation tools in OrCAD PSpice Simulator and the full suite of analysis tools from Cadence allow you to examine the behavior of your PDN and prevent common power integrity problems in advanced digital and analog systems.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.