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Design Guidelines for Shallow Trench Isolation Thermal Stress Minimization

What You Can Takeaway

  • What is shallow trench isolation (STI)?

  • How STI in manufactured transistors creates thermal stress.

  • The impact of thermal stress.

  • Design guidelines to help minimize STI generated thermal stress.

 Collection of silicon wafers

Magnified view of silicon wafers

The number of lives that have been saved due to the advances in vaccines and medications of the past few decades is immeasurable. Yet, there are cases where a drug can be very effective at solving one issue and also create a different one. For example, medications to thin blood are immensely successful in preventing blood clots that can lead to serious heart conditions. 

However, thinner blood makes you more susceptible to bleeding out quickly after a cut or some other serious lesion. Many times, the only option for these side effects is another treatment regimen as the elimination or control of the more dangerous ailment must be addressed favorably.

A similar situation where an undesired issue is created by solving a more significant one exists when building ICs, especially on the nanometer level. For many ICs, there are large numbers of transistors and within these devices, there are regions of silicon (Si), which contain smaller regions of SiO2 created by a process known as shallow trench isolation (STI). 

The side effect of this fabrication is that different coefficients of thermal expansion (CTEs) may exist between the Si and SiO2 areas. This shallow trench isolation thermal stress can negatively impact the transistor’s circuit performance. Let’s explore this process in greater depth and see what can be done during design to mitigate the degradation of circuit behavior. 

What Is Shallow Trench Isolation (STI)?

An example of STI is shown in the figure below.

Illustration of shallow trench isolation

Shallow Trench Isolation in CMOS Transistor

As shown in the figure, STI provides the necessary isolation between active regions in a transistor. This is achieved by creating trenches between the regions and filling them with an insulating material, typically SiO2. For many ICs, there are large numbers of transistors and the primary active region material is silicon (Si), which is separated into isolated blocks. Within these blocks, are the much smaller STI regions of SiO2. This process is effective; however, there is an unintended side effect. Thermal stress.

Thermal Stress: The Unintended Outcome of STI

Although necessary isolation is achieved, a variation in the coefficient of thermal expansions (CTEs), which define the relationship between material change in shape with respect to change in temperature, between the Si and SiO2 areas is formed. These variances are based upon proximity to the Si active regions and can alter the threshold voltages and carrier mobility within the device. As these parameters contribute to operation, circuit performance is impacted. 

The Impacts of STI Induced Thermal Stress

For electrical operation of the transistor, shallow trench isolation thermal stress primarily impacts the flow of carriers (electrons and/or holes) and the changes in threshold voltages. As with other crystal structures, Si exhibits the piezoresistive effect. When a mechanical stress or strain is applied the resistance of the structure changes. Although the voltage potential remains constant, the resistive modification results in a change in electron and/or hole flow. Threshold voltage variations are also instigated by mechanical stress and strain (as induced during board testing); however, the potentials are altered due to electron band modifications. 

Designing for Shallow Trench Isolation Thermal Stress Minimization

Shallow trench isolation thermal stress is a result of the fabrication process for your transistor wafers. Although eliminating the effects may not be possible, models that relate the electrical impacts with the application of thermal stress and strain can be created such that mathematical techniques; such as finite element analysis (FEA), can be used to solve for the effects. 

In order to compensate or mitigate the shallow trench isolation thermal stress, the design or gate level parameters, latency or delay and leakage power must be developed. These can be derived from the model parameters for stress and strain and threshold voltage by Taylor series or some other approximation method. 

IC design is a complicated process for moderate numbers of internal devices or transistors. For complex components that may have upwards of thousands of transistors or more, advanced software capabilities are required. This includes not only the mathematical methods, but also thermal and 3D analysis at the IC and board level, as shown below. 

:3D view of board with several ICs

Board level 3D analysis

The only PCB Design and Analysis company with a software platform that contains all of these capabilities is Cadence. With Allegro and the suite of tools able to integrate therein, including thermal analysis and 3D solvers, you can meet the IC design challenges for your project. 

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts