Applying Failure Oriented Accelerated Testing (FOAT) to Your PCB DFR

June 1, 2020

Cadence PCB Solutions

What You Can Takeaway

What is device reliability?
What is PCB Design for Reliability (DFR)?
How to use Failure Oriented Accelerated Testing (FOAT) for effective DFR.

Choosing the right path for PCB DFR

I think I was a pretty good kid. Now, it is possible that I may be the cause of one or two of the gray hairs on my parents’ heads, but overall I hope that I contributed to more smiles for them than sighs or worse. Nevertheless, I do vividly remember a few rare occasions when I had been up to some form of mischief and my mom always seemed to know about it. Yes, I can attest to the fact mothers do have an uncanny intuition.

Undoubtedly, intuition can lead you down the right path at times. However, when it comes to designing circuit boards for reliability, following a more logical course may be best. Although most designers may feel their designs are flawless, assessments of board performance once in the field which is typically required for risk management, show that some boards will fail prematurely. Therefore, logic dictates that design for reliability steps; such as those taken by reliability engineers be incorporated into the development process for your boards.

Let’s first take a look at device reliability and the role of the designer in the achievement of this objective or design for reliability (DFR). Then we can explore how to use a statistical failure rate (SFR) analysis method, failure oriented accelerated testing (FOAT), to guide our DFR efforts for not only reliability but also to optimize the efficiency of the board development process.

What is Device Reliability?

When someone refers to a friend or colleague as being reliable they are asserting that the person is dependable. In other words, if called upon they are confident the person will be able to do what they require. Broadly, the same is true for electronic device reliability. However, in science and engineering quantification necessitates that we are able to define reliability more precisely. Preferably, in terms of some observation or metric. In the figure below from [1], failure rates are used to illustrate the variation in electronic device reliability over its lifecycle.

Electronic device failure rate curves

The figure above shows what is known as a bathtub curve, which is a common device reliability representation of the three stages of failure over an electronic device’s lifecycle: decreasing, constant and increasing. Now, let’s see how we can use the failure rate as a metric on which to base a design for reliability strategy.

Designing PCBAs for Reliability

Observed failures are an excellent and precise metric for circuit board reliability once in the field. For risk management, this type of actual result is used as the catalyst to continually update the PCBA development process. However, this strategy of evolving reliability is not the most efficient as its success depends upon enough failures occurring such that risk factors can be identified and effective controls devised to mitigate them. It would be much better to be able to predict failure rates before deploying the boards.

The most often implemented means of assessing the reliability of a PCBA prior to deployment is testing. There are many types of circuit board tests. Some are non-invasive and can be done by manual or automated optical inspection (AOI). Other in-circuit tests (ICTs); such as flying probe (shown in the figure below) and bed-of-nails that test the functionality of components and circuits are helpful in assessing reliability, but require that design steps be included to facilitate their usage during manufacturing.

Flying probe PCBA testing

For example, the bed-of-nails test requires the specification of what is to be tested and the construction of a dedicated testing apparatus that will extend the turnaround time for manufacturing. There are also destructive testing techniques; such as Highly Accelerated Life Testing (HALT) and Comparative Tracking Index (CTI) testing that can be used to determine the amount of stress a board can endure before it is physically compromised.

Testing can undoubtedly be used to quantify when and if a board will fail in the field. The drawback is that most testing methods have costs associated with them; including unusable boards and time delays, which render them less than optimally efficient for determining board reliability. To help address this issue, there are design for reliability (DFR) simulations and FEA analyses that can be performed; such as EMC/EMI, power integrity (PI), signal integrity and thermal evaluations. Nevertheless, the accuracy of testing necessitates that it be performed in most cases where reliability is a primary consideration.

As shown above, device reliability requires collaboration between designer and contract manufacturer (CM). Therefore, DFR involves both performing tests or simulations and specifying criteria for physical testing.

DFR Based on Failure Oriented Accelerated Testing (FOAT)

Recently, there has been a thrust to improve the efficiency of DFR by adding a logical method of determining if physical testing, especially the costly destructive types, are indeed required. In order to justify a determination that this testing is not necessary requires that an alternative means of quantifying the failure rate be used. This includes the capability of accurately estimating the random statistical failure rate (SFR) that populates the constant failure rate portion of the life cycle curve from Fig. 2, above. A method that has emerged is failure oriented accelerated testing (FOAT).

FOAT forms the basis or foundation of a probabilistic approach to design for reliability or PDFR and has the following attributes:

Failure Oriented Accelerated Testing (FOAT) based DFR

Utilizes physical modeling
Quantifies the failure rate without physical testing
Is more cost-effective than physical testing
Allows for a range of conditions

In addition to the advantages listed above, FOAT can be used to determine whether or not to perform physical testing. Although computationally intensive, FOAT can be performed with capable mathematical modeling software saving both time and cost as opposed to physical testing methods. For example utilization of how FOAT can be applied; including model derivation, see [1].

PCBA DFR can involve a number of processes; including simulations and design specifications to aid your board’s testing. Moreover, the results of physical testing may require redesign to achieve an acceptable failure rate. The use of FOAT may minimize these requirements and improve the efficiency of your PCBA development process. In either case, an advanced PCB Design and Analysis package; such as Cadence Allegro is necessary to optimize your DFR process. Additionally, the use of DesignTrue DFM technology will enable you to generate initial designs that are manufacturable by your CM and save time and costs associated with excessive respins.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.