Signal Integrity Fundamentals in PCB Layout

July 23, 2021 Cadence PCB Solutions

Key Takeaways

  • Exploring signal integrity fundamentals

  • PCB layout techniques for good signal integrity

  • Layout tools and features that can help improve signal integrity

One of the defining characteristics of integrity is a consistent and uncompromising behavior that can be trusted. This is why integrity is also used to define the quality of a high-speed electrical signal in modern electronic devices and systems. We trust those signals to do the job that they were designed to do. However, signals that are degraded, or have poor signal integrity, may not accomplish their intended purpose. This can result in all kinds of problems in the electronics we design, from intermittent disruptions to outright failures.

To prevent these disruptions and failures, printed circuit boards need to be placed and routed according to specific design criteria to foster the best environment for transmitting high-speed signals. This involves every aspect of PCB design, including the parts used, the fabrication of the raw circuit board, and how the parts are arranged and connected together. To successfully design high-speed electronics, it is essential for the designer to understand signal integrity fundamentals.

Potential Problems Due to Poor Signal Integrity

The effects of interference on the operation of electronic devices can be pretty dramatic. For years, flight attendants urged us to shut down our cell phones or we were annoyed with radios that produced static instead of clear audio. Some older computers even radiated so much EMI that they were eventually taken off the market. However, the majority of problems caused by poor signal integrity are usually more subtle than that—there might be the occasional glitch in performance, data might get dropped, or the device may even fail to operate in extreme cases. All of these issues can often be traced back to signal integrity problems.

As signal speeds increase in our electronics, they are more susceptible to a variety of aggressive interferences. These can include signal reflections due to impedance mismatches, ground bounce, and crosstalk. If the circuit board is not specifically laid out to counter these problems, the signal degradation may continue until it no longer works as designed. Additionally, the circuit board must be designed so that it doesn’t create signal integrity problems for its own circuitry or nearby electronics. Before we look at how to design for these problems, let's first take a look at some critical signal integrity fundamentals. 

The Signal Integrity Fundamentals to Be Aware Of

Dense circuitry on a printed circuit board

Signal integrity fundamentals are critical to the success of circuit boards like this

A signal on a circuit board can have its quality degraded due to a number of different effects, and these can be categorized into different groups. Here are four main areas of poor signal integrity that you should be aware of.

Electromagnetic Interference (EMI)

High-frequency signals can radiate EMI if care isn’t taken with how they are routed on the circuit board. Not only can the length and configuration of the traces be a problem, but trace and via stubs can act as an antenna as well. Another source of EMI is the signal return path, which optimally should be on an adjacent reference plane. If the return path is blocked in any way, the signal will radiate even more noise as it seeks a path back to its source.

Unintentional Electromagnetic Coupling (Crosstalk)

High-speed traces that are too close together may inadvertently couple with one signal overpowering the other. This crosstalk can result in the victim signal mimicking the characteristics of the aggressor signal and not performing the task it was intended to do. Not only is this a problem with traces that are side-by-side, but also with traces that are routed in parallel on adjacent layers of the board. This type of crosstalk is known as broadside coupling and is why most circuit board designs alternate horizontal and vertical routing directions on adjacent layers.

Simultaneous Switching Noise (Ground Bounce)

With the number of components switching between high and low states on a circuit board, the voltage level may not return all the way to the ground potential as it should when it switches low. If the voltage level of the low state bounces too high, the low state of the signal may be falsely interpreted as a high state. When a lot of this happens simultaneously, it may result in false or double switching and disrupt the operation of the circuit.

Impedance Mismatch

Changes to the uniformity of sensitive high-speed transmission lines can cause signal reflections that distort the signal’s integrity. Traces routed without the proper attention to their impedance value will suffer changes to those values in different board areas depending on various conditions. To properly route impedance controlled sensitive traces requires a specific layer configuration, trace width, and clearance.

With the major problems in signal integrity defined, let’s now look at some PCB design techniques that will offset some of these issues.

PCB Layer Configurations and Component Placement

Signal integrity problems in printed circuit boards are often due to improper signal return paths. Not only does the return path need to be free of obstructions, but it needs to be on an adjacent reference plane layer for the best signal integrity. This configuration requires arranging the board layer stackup with dedicated layers for sensitive high-speed routing and adjacent reference planes in a microstrip or stripline configuration. A microstrip configuration consists of surface traces with a single plane underneath, while stripline traces are routed internally and sandwiched between two reference planes.

 Examples of different microstrip and stripline PCB layer stackup configurations

Microstrip and stripline layer configurations factor into signal integrity

While all signals will benefit from having an adjacent reference plane for a clear return path, it becomes even more important for sensitive signals that must be routed with controlled impedance. Calculating the dielectric width and constant along with the trace thickness will determine the trace width for controlled impedance routing. Since changing the board layer stackup or the materials used for PCB fabrication will alter these calculations, designers must determine the board layout configuration before the layout begins. These calculations will also vary depending on whether or not the impedance-controlled traces are routed using one of several microstrip or stripline configurations, as shown above.

With the board layer stackup configuration determined, the next step is to place the components on the board. Many high-speed circuits consist of multiple nets, which start at the source or driver pin on one component, continue through other parts, and then terminate at the load pin of the final component. These circuits are referred to as signal paths. To maintain their signal integrity, they must have their parts placed in sequence, as they are detailed in the schematic, to allow for the shortest point-to-point connection between pins. Other components, such as processors and memory chips, need to be spaced far enough apart to allow for all of their routing topologies, yet close enough for short connections. Here are some other key points of component placement to remember:

  • Follow the logic flow of the schematic when placing high-speed circuitry.
  • Place bypass capacitors close to each power pin of processor and memory devices.
  • Allow room for escape routing and bus routing.
  • Adhere to your assembler’s design for manufacturability (DFM) rules.
  • Ensure that the heat of hot-running components is dissipated.

With the parts on the board, the next step is routing.

Circuit Board Trace Routing and Reference Planes

3D view of differential pair routing from Cadence’s Allegro PCB Editor

Differential pair routing on a circuit board

At this point, you will be ready to start trace routing, but, remember that for good signal integrity, trace routing is closely tied to how the components are positioned. Escape routing, for instance, has to be carefully designed to ensure that all the signals are connected and that associated components, like bypass caps, are as close to their pins as possible. Many designs rely on via-in-pad for large pin-count BGAs to keep connections short and open up more room for routing.

With the parts placed in their most optimum position, you will be in the best position to route high-speed circuitry successfully. First, however, there are a few guidelines to keep in mind as you go:

  • Keep signal path traces short and direct.
  • Sensitive signals should be routed on internal layers and next to or between reference planes whenever possible.
  • Clock lines and other sensitive high-speed signals should be kept separate from other traces as much as possible. A good rule of thumb here is the spacing should be three times the trace width being used.
  • Keep differential pairs routed tightly together, and do not split the pair around obstacles like vias.
  • When routing groups of nets that have to all be matched in length, start with the longest connection first and add tuning turns to the others in order to match the first.
  • Do not route sensitive signals through noisy areas of circuitry, such as analog or power supply sections of the board.
  • Give yourself enough room for specific routing topologies, such as daisy chains, if needed.
  • Minimize the use of vias as much as possible to avoid their length and inductance, which may introduce more signal integrity problems.

In addition to the routing, you will also need to design the board’s power delivery network (PDN). Developing a clean PDN is imperative for power integrity, and it is also part of good signal integrity. It is also critical that you do not route high-speed transmission lines through areas of blockage on the reference plane. This can increase the amount of EMI the board generates as the signals wander around trying to find a clear return path back to their source. Blockages can include split planes, board cutouts, or dense areas of vias, as shown in the picture below.

A row of via antipads on a reference plane that has blocked the path for signal returns

Dense areas of vias can create a blockage for signal return paths on a reference plane

Designing a circuit board to maintain good signal integrity is a lot of work. Fortunately, there are some excellent features in your CAD tools that can help.

Layout Tools That Can Help Designers Maintain Signal Integrity

Today’s PCB design systems contain many helpful tools and features that will help you maintain good signal integrity in your designs. For instance, the Allegro PCB Editor from Cadence has a constraint system that allows you to set up rules for components, nets, high-speed nets, and even electrical attributes such as impedance and propagation delays. Additionally, the Sigrity Aurora tool offers in-design analysis capabilities allowing seamless integration of signal integrity, power, and electromagnetic simulations directly into your layout environment. Cadence also provides a suite of tools for circuit simulation, auto-routing, and signal analysis. 

For more information on high-speed design and signal integrity fundamentals, take a look at this E-book.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

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