The Planarization Process for Semiconductor Manufacturing

Key Takeaways

• Planarization is a critical process in semiconductor manufacturing that smooths irregularities on silicon wafers.

• Chemical Mechanical Planarization (CMP) is the dominant technique for achieving wafer planarity and involves mechanical polishing, chemical reactions, and precise metrology.

• While essential in the semiconductor industry, planarization techniques also find applications in optical component manufacturing, microelectromechanical systems, and so on.

Semiconductor devices have become a fundamental component in our technical world. At the heart of creating these tiny powerhouses lies something complex and delicate: the planarization process. Planarization is flattening or smoothing out a water surface by filling deep areas, etching the top of the surface, etc. This intricate process begins with a semiconductor wafer, which may have undergone numerous layers of deposition and etching, leaving its surface with unwanted bumps, troughs, and imperfections. To ensure the functionality of the integrated circuits, these irregularities are meticulously smoothed out in the planarization process.

The Chemical Mechanical Planarization Process

Chemical Mechanical Planarization (CMP), or Chemical Mechanical Polishing, has become the go-to technique for smoothing surface irregularities in silicon wafers. The CMP process is as follows:

1. Substrate Preparation: The semiconductor wafer is mounted on a carrier and introduced to the CMP tool.

2. Chemical Slurry Application: A chemical slurry, consisting of abrasive particles and chemical agents, is applied to the wafer's surface. The abrasive particles play a vital role in physically abrading the surface, while the chemical agents aid in material removal and control the selectivity of what is removed.

3. Mechanical Polishing: The wafer and carrier are pressed against a rotating polishing pad. The abrasive particles in the slurry, combined with the mechanical force, remove excess material from the wafer's surface. The control of pressure, rotational speed, and pad condition are critical factors in achieving the desired planarity.

4. Chemical Reaction: The chemical agents in the slurry react with the material being polished, aiding in its removal and preventing re-deposition.

5. Rinsing: After the polishing step, the wafer is rinsed with deionized water or specific rinsing solutions to remove any remaining slurry residue.

6. Post-CMP Cleaning: Additional cleaning steps may be performed to ensure the wafer is contaminant-free. Advanced cleaning techniques, such as megasonics or ultra-pure water rinses, are often employed.

7. Metrology and Inspection: The processed wafer is subjected to metrology tools and inspection techniques to verify its surface quality and thickness uniformity. This step involves measuring parameters like surface roughness, step height, and thickness distribution. 

Other Planarization Techniques: Spin-on-Glass (SOG)

Although CMP reigns on top, other planarization processes lead to the creation of planar wafers. Spin-on-glass (SOG) is a method that utilizes specifically made glass-based materials to achieve low-cost planarization. The main steps to achieve this are spinning and then annealing. In the spin phase, a siloxane-based organic SOG or silicate-based inorganic SOG material is dispensed onto a wafer. Then, the wafer is spun at high speeds. The material effectively seeps into gaps and irregularities in the wafer’s surface. The annealing phase (baking and curing) involves exposing the wafer to high temperatures for extended periods of time. This causes gradual evaporation of the solvent until the desired thickness is achieved, and also curing of the SOG film.

Other Planarization Techniques: Etching and Deposition

Etching is a planarization technique involving the selective removal of material from a semiconductor wafer's surface. Standard etching processes include chemical and plasma etching.

• In Chemical Etching, the wafer is exposed to a chemical solution that selectively dissolves the exposed areas of the material. The chemical composition and duration of the etching process determine its effectiveness. Wet chemical etching is precise but slower than other planarization techniques.

• Plasma Etching is a  dry etching process that uses reactive ionized gases (plasma) to remove material. Reactive ions bombard the wafer's surface, effectively etching away the exposed material.  Plasma etching offers high precision and control over the etching process.

Deposition

Deposition methods are used to add or grow thin films or layers of material onto a wafer's surface. Although used for various other steps in the semiconductor manufacturing process, deposition can also be applied to planarization. Common deposition processes are Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD).

• PVD involves the physical vaporization of a material, typically by heating it in a vacuum chamber. The vaporized material condenses onto the wafer's surface, creating a thin film. PVD is commonly used for metals and has applications in creating conductive layers and barrier films.

• CVD relies on chemical reactions to deposit thin films. Precursor gases are introduced into a chamber, where they chemically react to form a solid material on the wafer's surface.

Planarization Process Applications

Planarization, particularly CMP, plays a pivotal role in semiconductor manufacturing. It’s used in various applications of IC fabrication:

• Interlayer Dielectric (ILD) Planarization: CMP is employed to create a smooth, flat surface between metal or polysilicon layers, reducing the risk of electrical shorts and improving the performance of transistors.

• Shallow Trench Isolation (STI): CMP helps planarize the dielectric material between active regions, enhancing the isolation between transistors on a chip.

• Chemical Mechanical Planarization of Copper (Cu-CMP): Copper is often used as an interconnect material due to its superior electrical conductivity. Cu-CMP ensures a flat and uniform copper layer, reducing resistance and improving signal integrity.

However, planarization processes find applications beyond the semiconductors industry. Optical components, for example, take advantage of planarization techniques. In optical manufacturing, the process creates smooth surfaces on lenses and mirrors, reducing scattering and improving optical performance.

In the evolving world of semiconductor manufacturing, achieving flawless planarization is important. To streamline this intricate process, consider leveraging Cadence's Allegro X Advanced Package Designer. With Allegro X Advanced Package Designer, you can stay ahead in the competitive semiconductor market by gaining access to cutting-edge capabilities for all your IC packaging needs.