Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 76 ObjectRule Class-to-Class Table 9. Open the starter Object Rule table in the Lab-9_Virtex-7_to_DDR3 folder: objectrule_class_to_class_DDR3_SODIMM.xlsx 10. Review the Class-to-Class requirements for the DDR3 Interface. Type BYTE will be checked to SPC:5MIL_SPACE to the nets within the same Bytelane. Type BYTE will be checked to SPC:10MIL_SPACE between the Bytelane Groups. Type BYTE will be checked to SPC:15MIL_SPACE to nets assigned the Type classification ADDR. Type BYTE will be checked to 20MIL_SPACE to all other nets that have not been defined as a Class-to-Class relationship to BYTE. 11. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). Design Mapping Table 12. Open the design-specific Mapping file in the main design folder and review the On-Board DDR3 table (Name On-Board DDR3) at the bottom of the file: ACC_Workshop_mapping.xlsx 13. Locate the Name table DDR3_SODIMM; notice the LANE alias variable which is used in the Object table. This defines the number range for each Bytelane. 14. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv).