Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 75 Object Table 3. Open the starter Object table in the Lab-9_Virtex-7_to_DDR3 folder: object_grouping_DDR3_SODIMM.xlsx 4. Review the Net Groups/Diff Pairs for the Address, Clock Diff Pairs, and Data Bus in the table. Notice the use of a combination of simple ranges and Regular Expressions for Net selection for the Address Bus. Pay close attention to the Bytelane entries where the Net selection is using a combination of alias variables, Regular Expressions, and a SKILL function aliased to $CALCBITS. o The alias variable calls the SKILL function defined in skill.il and referenced in the ACC_DIRECTIVES.CSV file in the ./compiler folder. 5. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). ObjectRule Class-to-Class Table 6. Open the starter Object Rule table in the Lab-9_Virtex-7_to_DDR3 folder: objectrule_spec_DDR3_SODIMM.xlsx 7. Review the Type classification reference with Electrical rule assignment for the Address Bus (ADDR) and Data Bus (BYTE) in the table. Type ADDR simply adds a Stub Length and Max Via Count rule. Type DATA assigns explicit Pin Pairs from U1 to XP1 for all nets in the Bytelanes with an associated Relative Propagation Delay matched to 10mils (0:10). 8. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv).