Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 70 8. Define information in the Data rows: Header: Group Name Nets Type Rule Data: NetGroup SATA_BANK${LA NE} ${SATA_RX}[N,P]${LA NE} SATA_BAN KS PhysicalCSet:85_OHM _DP ${SATA_TX}[N,P]${LA NE} DiffPair ${SATA_X}${LAN E} ${SATA_X}[N,P]${LAN E} DP_PHASE Name column: i. SATA_BANK${LANE} assigns a Net Group name based on the selected Net members lane designation (SATA_BANKS<5:0>). ii. ${SATA_X}${LANE} assigns a Diff Pair name based on the selected Diff Pair members (SATA_RX<5:0>, SATA_TX<5:0>). Note: The above expression uses an Alias variable ${xxx} with xxx defined in the Mapping table. Nets column: i. ${SATA_RX}[N,P]${LANE} selects two nets per Diff Pair (SATA_RXN<5:0>, SATA_RXP<5:0>). ii. ${SATA_TX}[N,P]${LANE} selects two nets per Diff Pair (SATA_TXN<5:0>, SATA_TXP<5:0>). iii. ${SATA_X}[N,P]${LANE} selects two nets per Diff Pair (SATA_RXN<5:0>, SATA_RXP<5:0>, SATA_TXN<5:0>, SATA_TXP<5:0>). Note: The above expression uses Regular Expression single-character match using [x,x] and an Alias variable ${xxx} with xxx defined in the Mapping table.