Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 69 3. Enter the following information in the table: Name value SATA and Interface name SATA Note: The Mapping table Name and Interface need to match the interface name in the Object and ObjectRule tables. Update the other information in the header as required. 4. Define information in the Data rows as follows: Heade r: Type Alias Design Data: * SATA_ X SATA_RX:SATA _TX * SATA_ RX SATA_RX * SATA_ TX SATA_TX * LANE <{0-5}> 5. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). 6. Open the starter Object table in the Lab-8_Viper_ASIC_to_SATA folder: object_grouping_SATA.xlsx 7. Enter the following information in the table: Object name VIPER_TO_SATA and Interface name SATA Update the other information in the header as required.