Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 48 7. Enter the following information in the table: ObjectRule name VIRTEX-7_TO_DSP / Interface name Host Port / Units as mil Update the other information in the header as required. Enter HP_DATA in the Type column of the Data row. 8. Define information in the Header and Data rows after the Rule column: PROPAGATION_DELAY_PATH _TYPE PROPAGATION_DELAY_ MIN PROPAGATION_DELAY_ MAX L:S 0 4000 Group, Name, From Comp, To Comp, and Rule columns should remain empty. L:S in the PROPAGATION_DELAY_PATH_TYPE column, which indicates Longest/Shortest Pin Pair, should be checked to the Min and Max Propagation Delay. 9. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). 10. Open Constraint Manager and select Tools > Constraint Compiler. 11. Expand the acc_library folder; then select the folders Lab- 1_Rule_Spec_Sets and Lab-4_Virtex-7_to_DSP.