Allegro PCB Designer RAKs

Allegro Constraint Compiler

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Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 47 4. Define information in the Data rows: Header: Group Name Nets Type Rule Data: NetGrou p HP_DATA U2_HD{0-31}_AD.* HP_DAT A PHY:5MIL_3.5MIL;SPC:10MIL_SP ACE NetGrou p HP_REG_SE L U2_- HCNTL0_PSTOP_L PHY:5MIL_3.5MIL;SPC:10MIL_SP ACE U2_- HCNTL1_PDEVSEL_L NetGrou p HP_PCI_CNT RL U2_PCI_EN PHY:5MIL_3.5MIL;SPC:10MIL_SP ACE U2_-PCBE0_L U2_XSP_CS The first Data row in the Nets column: i. U2_HD{0-31}_AD.* selects 32 nets using a Number Range {...} and Regular Expression wildcard *. (U2_HD0_AD0, U2_HD1_AD1, U2_HD2_AD2, … U2_HD3_AD31) Type column is the Type classification name that will be used in the Object Rule table to reference the group of nets. Blank fields will not group the objects to a Type classification. Rule column calls out the Rule Specification and Rule Set to drive Physical and Spacing rules, separated by a semi-colon. 5. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). 6. Open the starter Object Rule table in the Lab-4_Virtex-7_to_DSP folder: objectrule_spec_Host_Port.xlsx

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