Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 24 Object Rule Table Example: ObjectRu le MY_OBJ_RU LE Revision 1 Units mil Interface PCI Manufacturer Created by Cadence Header Relative Prop Delay Prop Delay Group Name From Comp To Comp Delta:Tolerance Max Data NetClass HS- PORT_DATA Part=U20 Part=U21 :50 2500 NetClass HS- PORT_ADDR Part=U20 Part=U21 :100 4000 End Results: Generates Match Group HS-PORT_DATA with the Pin Pairs between U20 and U21 for Net Class HS-PORT_DATA with the following rules: o Relative Propagation Delay Tolerance = 50 o Max Propagation Delay = 2500 Generates Match Group HS-PORT_ADDR with the Pin Pairs between U20 and U21 for Net Class HS-PORT_ADDR with the following rules: o Relative Propagation Delay Tolerance = 100 o Max Propagation Delay = 4000 Relative Propagation Delay with an empty Delta field will match all Match Group members within the Tolerance. o Setting the Delta field to 0 will match all Match Group members to the longest pin-to-pin Manhattan length within the defined Tolerance (+/- Tolerance). o Setting the Delta to anything other than 0, on a specific net, will be treated as a +/- offset to the member who yields the longest pin-to-pin Manhattan