Allegro PCB Designer RAKs

Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 23 Column Header Descriptions Group or Kind Type of group defined in an Object table or Net / XNet (leave blank if not required) Name Name of group defined in an Object table (required if Group or Kind is specified) or existing Net / XNet name existing in the design Note: Assigning rules to existing Net / XNet design objects are supported. Note: Assigning a rule to a Net which is a member of an XNet will apply the rule to the XNet. Type Type classification assigned to objects in an Object table From Comp Used to generate Pin-Pair assignments - Reference Designator or Reference Designator and Pin Number (Refdes.Pin#) To Comp Used to generate Pin-Pair assignments - Reference Designator or Reference Designator and Pin Number (Refdes.Pin#) Rule Rule Specification and Rule Set reference for the selected objects Rule Specification Name:Rule Set Name Can also reference existing Constraint Set in Layout (PhysicalCSet:, SpacingCSet:, etc.) Multiple Rule Specifications or Constraint Sets can be listed separated by a semicolon ";" Constraint Name Constraint Attribute name (MIN_LINE_WIDTH, LINE_TO_LINE_SPACING, LINE_TO_THRUVIA_SPACING) or Keyword mapped alias to Constraint Attribute name (Width:Min Line, Line To Line, Line To Thru Via) Note: Hovering over the header in Constraint Manager will report the Constraint Attribute name in the Datatip. Note: Custom Keyword mapping in the Directive Global section of CDS_ACC_DIRECTIVES.CSV (Cadence Default) or ACC_DIRECTIVES.CSV (User Defined) Note: Match Groups will be automatically created If Relative Propagation Delay rules are specified.

• Cover
• Purpose
• Audience
• Terms
• Overview
• Benefits of ACC
• Functional Overview
• Table and Specification Format Overview
• Mapping Name Table
• Object Table
• Rule Specification Table (Rule Sets)
• Object Rule Table (Object Rules)
• Object Rule Table (Class-to-Class Rules)
• User Interface and Data Query
• Validation and Apply Constraints to Design
• Reporting
• ACC Lab Exercises
• License Requirements / Workshop Structure
• Lab 1-1: Rule Specifications Structure Review
• Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1)
• Lab 1-3: DSP (RefDes U2) To HS Connector (RefDes U4)
• Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2)
• Lab 1-5: VIRTEX-7 (RefDes U1) To PCIe HSIO (RefDes J3)
• Lab 1-6: Viper (RefDes U34) To PCIe CONN (RefDes J1)
• Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional
• Lab 1-8: Viper (RefDes U34) To SATA Connectors (RefDes J2,J7-9,J11,J12)
• Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1)
• Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35)
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