Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 11 o rule_spec_Elec_DiffPair_starter.xlsx (Electrical domain) • Differential Pair Worksheet o rule_spec_Elec_PropDelay_starter.xlsx (Electrical domain) • Propagation Delay Worksheet Object Rule Table (Object Rules) o objectrule_spec_starter.xlsx Object Rule Table (Class-to-Class Rules) o objectrule_class_to_class_starter.xlsx Below is an example of an ObjectRule table: ObjectRul e HS_BUS Revision 1 Units mil Header Prop Delay Group Name From Comp To Comp Min Max Note Data NetClass HS_TX Part=U1 Part=U2 500 2500 1 NetClass HS_RX Part=U1 Part=U2 500 2500 Note 1 TX Lines should be routed as short as possible End Comment Rules in this file are to be used for expansion card slots only. Constraint tables (Object, ObjectRule, and Rule) mapping precedence is as follows: Mapping Name table and Constraint table of the same name Mapping Name table name matching the "Interface" key value in the Constraint table