The PCB can be no better than the underlying . A lot of boards end up as scrap or are only partially useful due to improper footprints. Extra design cycles to fix these preventable problems can move the product’s break-even point out as the extra engineering has to be paid back through additional sales. Flaky footprints out in the wild can end up causing warranty and recall issues that undercut the entire product launch. This is one of those cases where an ounce of prevention equals a ton of cure.
The trouble is the same everywhere and by “everywhere”
, I mean all of the start-ups that have hired me. The library is a hodgepodge of different naming conventions and methods. It takes less time to create a new footprint than to go through the stuff extracted from the service bureau or the consultant. The library dump ended up being just that, a dump. It is unlikely that you will get a week up front to update the whole list but you will occasionally get a little down time between submitting some preliminary work and getting the feedback. Use those cycles to fix one part at a time.
Image credit: Reference Designer - showing the nominal (B) size of a common cap that is also known as an 0603 in the IEC nomenclature and 1608 in the metric system.
It is a big job that starts with that one small victory. To get things started, I would recommend a phased approach. Each of these phases should be sequestered in a separate directory. Call them “Archive,” “Candidate,” and “Known Good” footprints or something like that. It might make sense to restrict write-access to the directory with the golden parts. If you know from the start that you will never have time to put a dent in the library, it may be wise to outsource this to a consultant or a service bureau. There are also a number of companies that will generate new footprints for you at a reasonable cost. Whatever means you use, breaking the project into tasks give a sense of accomplishment as one part ends and another begins.
Phase one: Get a handle on what you have by exporting the library from the existing board or boards and going through them making sure the padstack and footprint names are unique and traceable. That is it; rename everything that does not follow the standard. Phase one is taking inventory and setting the stage for the schematic symbols to be scrubbed with the correct “JEDEC” names. If your symbol names already follow a process, move along.
Phase two: Hopefully, you have data sheets or Source Control Drawings to compare with the existing footprints. The company database or the internet might help, but asking around and letting on that you are tackling the elephant in the room should get you a little sympathy. Phase two is bringing all of the components up to standards. If you are sharing this task or even if you are not, writing down the preferred practices will keep you on track.
Phase three: Independent checking. Enlisting other people to help isn’t easy, but you might be too close to the action to catch an error. For instance, vendors for BGA packages usually show the pin map as seen from the bottom while you create it with Superman’s X-ray vision seeing the pins through the body of the device. It may look good but will not work if you did not mentally flip the part.
Things to consider when checking a device footprint:
- File name: It is not just an 0402 cap According to IPC-7551, we would call it CAPC + Body Length X Width X Height + L Lead Length or CAPC100X50X50L30B for short.
- Pin one and all of the corresponding pins must match the data sheet and/or . Orientation marking should be consistent.
- Component outline. I like to make the assembly layer at the nominal size and the silkscreen just outside of the maximum size so it is visible with the component in place. All silkscreen items need a plausible line width and clearance around solderable areas.
- Dimensions should go on the nominal size and follow the general style of the datasheet to make it easy for the checker to match them up. I catch most of my mistakes while doing the dimensions.
- The unit of measure should be metric. It is almost certain that the datasheet provides metric values that also help tie into the footprint naming conventions.
- Shapes that define the X, Y and Z dimensions should also be set to the maximum allowable size. This is what is used to generate the MCAD file for fit checking.
- The origin is usually the center of the component but can be at pin one. Pick and place machines typically handle the part from its center so that is best for the XY placement file.
- Design For Assembly: This takes time to set up, but the DFA properties and shapes are great for maintaining minimum clearance on crowded boards. Not only is this helping in real time placement, but it also is very handy for design verification since you can prove that any non-compliant placement will be flagged with a.
- Padstacks: The vendor usually provides a land pattern but not always. An SMD pad needs the metal, mask and paste layers defined. The soldermask is either larger or smaller than the metal by 75 to 100 microns depending on the pin density. IPC guidelines are useful for generating padstacks based on the lead geometry.
- Through holes get the drill size and tolerance along with capture pads for outer and inner layers plus mask. The last time I created negative artwork was in the 1990’s so I don’t bother with anti-pads or thermal relief. That geometry is driven by the design rules and is manifest by the copper pour.
- Reference Designators: I think the best initial location is right over the part. If you place it above or next to the component, it will end up covering the next part over at board level.
Having components that have been road tested and are traceable will cut down on iterations and may help you sleep better after tape-out day.
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