# Can You Really Eliminate Far-End Crosstalk (FEXT) in a PCB?

There are two forms of crosstalk: near-end crosstalk (NEXT) and far-end crosstalk (FEXT). The former is observed on a victim interconnect near the driver, and the latter is observed on a victim interconnect near the receiver. Each of these has an inductive and capacitive contribution, meaning the strength of crosstalk is determined by the mutual inductance and mutual capacitance between two traces.

NEXT cannot be suppressed by judicious selection of dielectric material or trace geometry; it will always occur and can only be suppressed with greater spacing, parasitics reduction, or some kind of shielding structures.

What about FEXT? If you look at the equation for the strength of FEXT, there is a special mathematical case in striplines where FEXT is zero. Is this something that would be observed in reality? We’ll break this down in this article.

## Crosstalk Coupling Coefficients

Crosstalk coupling coefficients can be derived by calculating the voltage and current placed on a victim trace due to mutual capacitance and mutual inductance between two traces. The crosstalk coupling coefficients used to calculate this voltage and current are defined by summing the capacitive and inductive contributions to the voltages induced on the victim line. The end result is to get a ratio that defines the near-end voltage (V-NE) and far-end voltage (V-FE) to the signal level on the aggressor line.

Without going through the entire derivation, the FEXT and NEXT coupling coefficients are defined below:

*NEXT and FEXT coupling coefficients.*

The “M” subscript denotes “mutual”, meaning the mutual capacitance and mutual inductance. The “L” subscript denotes “line”, meaning the line’s inherent capacitance and inductance. When these NEXT and FEXT are larger, the strength of the crosstalk signal is also larger. A designer’s goal in high-speed PCB design is to suppress crosstalk as much as possible and ideally eliminate it.

Note that, for NEXT, the expression assumes that the parallel length between the traces is equal to or longer than the velocity-rise time product. If this ratio is less than 1, then NEXT will be reduced by a factor:

*NEXT scaling factor.*

For FEXT, we have a difference between inductive and capacitive contributions in the right side of the expression. This means there is a possibility to eliminate FEXT if the following relation is satisfied between the aggressor and victim transmission lines:

*If the relative inductive and capacitive contributions to FEXT are equal, then they cancel each other and FEXT = 0.*

It is now a fair question to ask: what is needed to engineer two transmission lines such that their FEXT coupling coefficient is equal to 0? It depends on whether we are looking at microstrips or striplines, as well as whether we have coplanar routing as might be used in a board with a thicker dielectric layer.

### FEXT in Striplines

The special case of FEXT cancellation could conceivably arise in striplines. In particular, we could have the above relation satisfied if the following requirements are satisfied:

- The impedances of the aggressor and victim transmission lines are equal
- The dielectric properties of the materials above and below the striplines are linear, isotropic, and homogeneous

#1 is only satisfied in the case where the laminate materials used above and below the layer containing the striplines have exactly the same Dk value. This does not always occur; PCB stackups might use alternating core-prepreg layer pairs that do not have the same Dk values, and so there would always be some FEXT.

#2 is only true at low frequencies, meaning when the rise time is slow enough that the relevant bandwidth does not span far into the GHz range. If this condition and #1 are satisfied, then it is possible for FEXT to be eliminated. This does not always occur in reality; instead the best way to reduce FEXT should it occur is to space out traces and bring them closer to their reference plane.

### FEXT in Microstrips

If we just look at a pair of microstrips, it should be clear that the environment around the traces where the electromagnetic exists will never be homogeneous, so there will always be some crosstalk. For two microstrips running in parallel, you cannot have FEXT = 0 unless the Dk value for the dielectric and the solder mask were equal to 1.

But what about the use of more elaborate routing and transmission line designs? As it turns out, there has been some research into the use of stubbed microstrip transmission lines to create destructive interference between the capacitive and inductive contributions to crosstalk. An example discussed by Intel and two references looking at this problem are shown below.

*Stubbed transmission lines used for FEXT suppression.*

Details on the design of these structures can be found in the following references:

- Kunze, Richard K., Yunhui Chu, Z. Yu, San K. Chhay, Mauro Lai, and Yanjie Zhu. "Crosstalk mitigation and impedance management using tabbed lines." Intel white paper (2015).
- Lee, S. K., K. Lee, H. J. Park, and J. Y. Sim. "FEXT-eliminated stub-alternated microstrip line for multi-gigabit/second parallel links." Electronics letters 44, no. 4 (2008): 272-273.

The basic idea in this structure is that the stubs along each line artificially increase the mutual capacitance between two lines without greatly increasing their mutual inductance. In this way, the relative capacitive and inductive coupling fractions are brought closer together, and their difference becomes closer to 0. The important factor here is to engineer the size of these stubs such that they do not create excessive S11 along the length of these lines due to potential impedance discontinuities. As long as the stubs are not too wide compared to the distance traveled by a digital signal during its rise time, then they will not create excessive S11.

When you need to evaluate the strength of NEXT and FEXT between interconnects, you can use the integrated signal integrity tools in Allegro PCB Designer with Sigrity from Cadence. Only Cadence offers the best PCB design and analysis software that includes industry-standard CAD tools, powerful routing features, and much more.

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