What You Can Learn
Electromigration (EM) analysis in VLSI design refers to optimizing IC interconnects to prevent electrochemical growth.
The processes governing EM in a PCB is different from what occurs in an IC, and the solutions used in each domain are different.
VLSI optimization requires balancing signal speed with current density.
You’ll need to design this IC and these boards to suppress electromigration.
Failure mechanisms are plentiful in electronics, both at the IC and PCB level. An insidious form of failure in ICs, and high voltage PCBs, is electromigration (EM). This is an electrochemical effect in PCBs and, while it is due to scattering in ICs, designers need to consider metal migration and growth mechanisms when creating their designs. The goal is to ensure reliability at the IC and PCB levels, thereby extending lifetimes as long as possible.
As integrated circuits continue to get smaller, the probability of failure in VLSI increases. Ever since the 90 nm node, EM has been a problem and needs to be optimized alongside current density and timing. EM analysis in VLSI. Clearances and thicknesses of traces can be defined as design rules in VLSI, which helps designers prevent EM and failure during operation. Here’s how to analyze EM in VLSI design.
What Is EM in VLSI?
EM is an electrical effect whereby electrons on an IC interconnect give some momentum to the atoms that make up the wire. This happens through low energy collisions and subsequent scattering. As a result, the interconnect deforms over time as atoms are moved along the interconnect towards the cathode. This causes pits to appear in the wire closer to the anode, and small metal bumps begin to grow along the surface of the wire closer to the cathode.
This occurs at very high current densities (usually >10,000 A/cm2), and the rate of EM is higher when the current density in the wire is larger. This means that EM is a runaway process. As EM occurs in one region of the wire, the cross-sectional area decreases, and the current density increases. As a result, the rate of EM also increases. Over time, more metal migrates at a faster rate, and the process eventually ends with a short circuit or an open circuit.
The open circuit failure occurs when the metal along the wire is totally depleted and leaves behind a void in the wire. In the case of a short circuit, a dendrite grows off the wire until it bridges the gap between two conductors. In both cases, the component fails to operate correctly and must be replaced. In VLSI, a short-circuit failure is more likely to occur than open-circuit failure simply because interconnects are closer together.
Hillock and void growth during EM.
There is also another process that contributes to EM: thermal runaway. EM follows an Ahrrenius process with some defined activation energy, which means the rate of migration increases as the interconnect temperature increases. As EM proceeds, the region with depleted metal has higher current density and higher resistance, resulting in a higher temperature as the chip operates.
What About PCBs?
EM also refers to a failure mechanism in PCBs that leads to short circuits in high voltage boards. However, EM in PCBs is an electrochemical effect that leads to short circuits due to bridging.
In a PCB, some residual salts on exposed metal can dissolve into an electrolyte solution if water condenses on the metal. A high electric field between two conductors (i.e. at high voltage or close spacing) can drive an electrochemical reaction, which causes growth of metal salts. These dendrites can grow and eventually bridge the gap between the two conductors, causing a short circuit.
The solution here is similar to that in VLSI: provide sufficient spacing between two conductors at different potentials, or design the layout so that only common-mode conductors are placed close together. This is one reason creepage standards are provided by IPC (specifically, IPC-2221). Note that EM between conductors in a PCB is also a thermally driven process, although the same thermal runaway problem does not occur during dendritic growth.
Optimizing IC Interconnects to Prevent EM
Like most problems in engineering, designing for reliability in electronics is all about weighing the tradeoffs involved in different design choices. In terms of VLSI, the natural solution is to simply increase the width of a trace. This would ideally reduce the current density below the threshold for EM. However, the wire width is not the whole story, and there are other important aspects of an IC that need to be optimized.
Because the propensity for EM depends on the current density in a wire, it also depends on the switching rate for a signal in the interconnect. When a digital signal switches, there is a momentary large burst of current, and minute amounts of EM can occur during such a large burst of current. Over time, EM accumulates over trillions of switching events. Furthermore, when the rise time for the signal is shorter, the peak current during switching is larger, which leads to more EM as the chip operates.
The effects of EM on mean time to failure (MTTF) are summarized in Black’s law, which can then be used to optimize the design of an integrated circuit.
Black’s law for EM analysis in VLSI.
Here are some of the challenges involved in interconnect optimization during VLSI design:
Increasing interconnect width decreases resistance and current density, but it increases capacitance (lowers rise time).
Decreasing spacing between interconnects aids integration, but it increases potential crosstalk coupling.
Lowering the rise time decreases crosstalk coupling and peak current density, but it requires making the chip physically larger.
Reducing signal level decreases current density and crosstalk coupling, but it reduces SNR levels and places smaller tolerances on power integrity.
Of course, these four problems cannot be solved in isolation. But there are software tools available that can help you find a balance when designing interconnects in VLSI.
Whether you need to layout a new circuit board or IC, you can adopt results from EM analysis in VLSI design with a powerful PCB design and analysis software package. The Clarity 3D Solver from Cadence provides a suite of 3D EM solving and co-simulation features in one fantastic product. Allegro PCB Designer and Cadence’s full suite of analysis tools integrate with the AWR Connected toolset for complete PCB and IC design and analysis.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.