When designing a mixed-signal system, one of the important points to consider is the selection of an ADC and/or DAC to convert between digital and analog signals. Like most components, these parts have a range of specifications that need to be balanced to ensure system performance targets can be met. When looking for an ADC for a particular application area, it’s common to search by ADC specifications, but components with common specifications are commonly categorized as different types of ADCs.
If you’re reading a datasheet for a microcontroller, ADC IC, or a module with an ADC, it’s likely the only information provided is the resolution, bandwidth, and the type of ADC. While precise measurements usually require going deeper into the capabilities of the ADC circuitry, it’s important to know how these parts are categorized for use in mixed signal systems. In this article, we’ll look at how different types of ADCs are categorized in terms of their sampling capabilities, as well as the internal architecture of these components.
Types of ADCs and Their Characteristics
In general, there five five different types of ADCs packaged as integrated circuits for use in electronic systems:
- Successive approximation (SAR)
These ADCs all perform the same function, but with different converter circuit architectures and capabilities. Two of the primary capabilities where these types of ADCs differ are in their sample rate and resolution, which arises due to the different conversion circuitry used in these components. The table below summarizes the main capabilities of these different types of ADCs.
In terms of packaging and usage in a PCB, there are very minor differences between these types of ADCs. They are all available in standard packaging types, they follow similar mixed-signal PCB layout guidelines (including best-practices for mixed-signal grounding), they use standardized serial interfaces or parallel bitstreams to provide a digital output, and they may be multichannel devices that can be used with multiple input analog signals.
We’ll start with this type of ADC as it is arguably the most common. This architecture tends to operate at low frequency and uses a summer-integrator-comparator architecture with a reference voltage source to generate an output bitstream.
Sigma-delta ADC block diagram
The comparator in the above block diagram outputs bits based on whether successive outputs from the integrator are higher or lower than the output value from the previous time step. In effect, these circuits are entirely limited by the comparator portion, which must saturate as the inputs change. Therefore, these systems can be somewhat slow compared to other architectures that generate the output through a counter or through multiple comparators in parallel.
Successive Approximation (SAR)
This is also among the most common type of ADC. More advanced microcontrollers or processors may integrate an SAR ADC into the component package, particularly in microcontrollers marketed as mixed-signal SoCs. The architecture of an SAR ADC is shown below.
SAR ADC block diagram
The input section uses a sample-and-hold (SAH) circuit to track the input signal at each clock pulse. The comparator then tracks when the input increases and passes this to the Control block. A series of N comparisons in parallel is used to determine each of the N bits in the output bitstream. Therefore, an SAR ADC needs at least (N + 1) clock cycles to convert the analog input to a digital number. The output could be provided as a serial bitstream or on a parallel bus with a latency of one clock cycle.
These ADCs are used in precision measurement equipment that requires even response over broad bandwidths, such as oscilloscopes and high-bandwidth DAQ units. Although they do not have the highest resolution, they still provide very accurate measurements when noise is sufficiently low. 16-bits is a typical resolution value, with sample rates reaching ~1 GHz. The architecture of these ADCs can be quite complicated, involving multiple stages with sub-ADC and DAC blocks in parallel. The parallelized architecture makes these ADCs very fast with latency of only a few clock cycles.
These ADCs are an upgrade compared to a pipelined ADC, and they are often used for RF measurement and direct conversion applications. The tradeoff with these products is their lower resolution, with bit depths of no more than about 10-12 bits available. Flash ADCs use a large parallel bank of comparators with wideband low-gain preamps followed by a latch. The parallel structure of these ADCs in the analog input stage of these components provides even higher latency than a pipelined ADC, reaching as low as 1 clock cycle.
These ADCs have low sample rates, but they have a simple structure with high resolution, offering very accurate readout of DC voltage levels or low-frequency analog signals by adjusting a reference voltage and oscillator in the internal timing and control circuit (see below). Although these ADCs have low speed and sample rates, they offer high resolution that is only limited by the feedback loop on the input analog comparator. This type of ADC was initially a breakthrough for use in digital multimeters.
Dual-slope ADC block diagram [Source: Hank Zumbahlen, with the engineering staff of Analog Devices, in Linear Circuit Design Handbook, 2008]
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