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John Park Webinar: Is It the Age of the Chiplet?

Author Cadence PCB Solutions

I first started paying attention to 3D packaging many years ago. Every year there was a conference at the Hyatt in Burlingame on the topic. Everyone was convinced that 3D packaging was coming really soon. Here is a Semiwiki post from 2014 that I wrote about that year's conference. Herb Reiter, who I worked with at VLSI Technology when we were both in the organization that handled licensing and M&A, was driving the segment for the Global Semiconductor Alliance (GSA). By the way, before GSA was GSA, it was FSA, the Fabless Semiconductor Alliance. That was originally created since the SIA (the Semiconductor Industry Alliance) wouldn't allow fabless semiconductor companies to become members since they were not "real" semiconductor companies. Now that the top semiconductor company lists are filled with fabless companies, that seems almost amusingly...short-sighted.

But 3D packaging seemed to be like Gallium Arsenide. Always about to break through to the mainstream, but with the emphasis on "about to". The GSA ran out of patience and Herb had to find a new gig. The reality was that 3D packaging was one of those boil-the-ocean technology changes like the switch from 8" to 12" wafers in manufacturing. Everyone has to move or nobody can. For packaging, the technology needed to be available, but also design tools, and manufacturers ready to roll at volume...and low cost. The first 3D chips were, I believe, Xilinx's high-end arrays where they put four die on a silicon substrate. But that technology was only appropriate for chips that were selling for thousands of dollars each.

Going Mainstream

The advantages of 3D packaging were well understood. The competition was continuing to do things the old way, to integrate everything onto a single system-on-chip (SoC). There were several potential advantages of the 3D approach:

  • They had great branding in the phrase "More than Moore" and Moore's Law was perceived to be slowing
  • You didn't have to build the whole chip in the most advanced node, only those parts that could take advantage of it
  • You could mix into your design die from processes that were incompatible with the basic logic process, such as DRAM or RF
  • Analog and RF were difficult or impossible in the FinFET era, and didn't benefit at all in terms of area from scaling, so the SoC approach didn't really work for designs with a big analog component
  • The yield of a given silicon area built as a huge chip was a lot lower than the same silicon built out of several separate die and then put together with 3D packaging

But the disadvantage was basically a single bullet:

  • It was too expensive

The challenge was a sort of chicken-and-egg problem: 3D packaging would only be used for high-volume manufacturing when it was cheaper than monolithic integration, or alternative approaches like package-on-package (PoP). But 3D packaging would only get cheap once it was in high-volume manufacturing. Semiconductor wafer fabrication has this problem, too, of course. I did a presentation internally at Cadence in February last year called EDA 201 and TSMC's Tom Quan was my co-presenter and showed up with a 5nm prototype wafer. It was the first 5nm wafer I'd ever seen except in photographs. We speculated that it was a multi-million dollar wafer. If all 5nm wafers were going to cost millions of dollars, nobody would buy them. But everyone knows that once the teething troubles are sorted out and there are tens of thousands of wafers per month running, the costs would come down. The entire semiconductor industry, in fact, depends on this trajectory being true.

At HOTCHIPS last summer, I noticed that many of the "chips" being presented as hot were, in fact, 3D-packaged systems. I wrote about some of them in my post HOT CHIPS: Chipletifying Designs. That covered designs from AMD, Intel, NVIDIA, HP, and more. It seems that 2019 was finally the year that More than Moore became real.

The key to the mainstream turned out to be the catchily named fanout wafer-level packaging (FOWLP) and the move to use it by the mobile industry, the only industry with enough volume to completely shift the whole manufacturing ecosystem. Once mobile provided the volume, the economics changed and the technology could be used for lower volume markets, too. Other technologies, such as Intel's Foveros, have also come into use. Various interposer based approaches have become mainstream, too. It no longer seems risky or idiocentric to put more than one die into a package.

Chiplets

Here is a clip from an AMD presentation at HOTCHIPS, which echoes many of the bullet points I made above:

The die that are used to assemble these systems are often called chiplets, since they are less than a chip and not really designed to be used on their own. All of the designs presented at HOTCHIPS had chiplets that were created specifically for that design. Instead of building a big monolithic SoC, three or four chiplets were designed and then put together with advanced packaging.

One interesting question is whether the semiconductor ecosystem will switch to being chiplet-based. Instead of a system consisting of either a monolithic SoC, or separate SoCs put on a PCB, could it be assembled out of chiplets purchased from different semiconductor manufacturers. Cadence actually produced one such chiplet as a test chiplet for die-to-die (D2D) interconnect. You can read about that in my post Die-to-Die Interconnect: The UltraLink D2D PHY IP.

There are clearly some technical and standards issues to making this work, but the biggest problem is likely to be the business model. For very-high-volume designs, nobody is going to be holding enough inventory to take an order out of the blue for 100M parts. But for smaller volumes, somebody needs to hold inventory and get compensated for doing so. That could be semiconductor companies, IP companies, traditional distributors of components, or even brand new companies created to serve this market. Time will tell how this shapes up.