Decoding RF-CMOS Performance Trends

Key Takeaways

• Continuous technology scaling enables advanced nanometer CMOS technologies for RF and mm-wave applications up to 100 GHz, facilitating complex system-on-chip implementations.

• Techniques like transistor body biasing and flipped well LVT transistors enable low-voltage operation and improved performance in RF CMOS circuits.

• Modifying circuit topologies and adopting transformer-based power combining techniques address the challenges of low-voltage RF circuits, enabling high-performance operation at lower supply voltages.

Due to RF-CMOS performance trends, many circuit blocks such as this RF mixer are being further miniaturized and operating at higher frequencies

Radio frequency (RF) CMOS technology has revolutionized wireless communication systems by integrating RF and digital circuitry on a single chip. Over the years, new RF-CMOS performance trends for design and fabrication processes have led to significant improvements in performance, enabling the development of more efficient and cost-effective wireless devices. We will explore RF-CMOS performance trends and discuss the factors driving its growth.

General RF-CMOS  Performance Trends

Continuous technology scaling has contributed to the success and widespread use of CMOS integrated circuits (ICs), enabling improved transistor performance at RF frequencies. As a result, advanced nanometer CMOS technologies are now suitable for various applications up to 100 GHz, including 5G, automotive radar, and imaging. Compared to traditional compound semiconductors or heterojunction bipolar transistors (HBT), CMOS offers greater integration capabilities, facilitating complex system-on-chip (SoC) implementations. Below are some of the general technology advancements driving these trends. 

• Shrinking Technology Nodes: One of the primary factors driving the performance improvements in RF-CMOS technology is the continuous scaling of technology nodes. As the semiconductor industry moves to smaller process nodes, the transistor dimensions are reduced, resulting in higher device speeds, improved linearity, and reduced power consumption. This rf-cmos performance trend allows RF-CMOS circuits to operate at higher frequencies, enabling the realization of advanced wireless communication systems.

• Enhanced Device Modeling and Circuit Design: Accurate device modeling and circuit design techniques are crucial in optimizing RF-CMOS circuits' performance. Researchers and industry experts have made significant progress in developing models that capture the behavior of RF-CMOS devices at high frequencies, considering the non-linear effects, parasitic components, and process variations. 

• Integration of RF Front-End Modules: Integrating RF front-end modules (RF FEM) with CMOS technology has been a significant trend in recent years. RF FEMs, which include power amplifiers, low-noise amplifiers, filters, and switches, are crucial for signal transmission and reception in wireless devices. 

Specific RF-CMOS Performance Trends in Design

The scaling of CMOS technology has also led to a continuous decrease in the supply voltage, making it feasible to utilize CMOS in applications like wireless sensor networks (WSNs) and the Internet of Things (IoTs). However, sub-1-V supply voltages present challenges in circuit design, particularly in RF/mm-wave frequencies. Overcoming these voltage limitations requires the use of nonstandard circuit topologies and specific techniques, discussed further below.

Transistor Body Biasing

A recent RF-CMOS performance trend involves utilizing the body biasing technique to adjust the threshold voltage (V_T) of an n-MOS transistor. This technique involves modifying V_T based on the voltage (V_BS) between the body and the source, using the well-established equation:

Through V_BS manipulation, the transistor can operate at a reduced bias voltage while maintaining similar characteristics in terms of gain, linearity, and noise, proving effective for RF operations.

Furthermore, the effectiveness of the body biasing technique is significantly enhanced in FD-SOI CMOS platforms. This is due to the platform's wider variation in V_T compared to bulk technologies and its lack of leakage currents.

Flipped Well LVT Transistors

Flipped-well low-VT (LVT) transistors offer an alternative approach. These transistors utilize an n-well body and a p-well body for n-MOS and p-MOS devices, respectively. In this configuration, the BOX layer functions as a second gate oxide, and the body acts as a gate terminal, which enables VT adjustment through the body voltage.

The body gain factor, which represents the sensitivity of V_T to the body voltage, is approximately four times higher in flipped-well devices compared to traditional bulk technology, making them even better suited for low-voltage CMOS integrated circuits (ICs).

RF Circuit Topologies for Low-Voltage Operation 

Another meaningful RF-CMOS performance trend is geometrical scaling, allowing nanometer CMOS to achieve high performance with transition frequency and maximum oscillation frequency reaching 200 GHz or higher values. However, this improvement comes at the cost of a significant reduction in transistor breakdown voltage (BV) and maximum supply voltage compared to equivalent HBT BiCMOS technologies.

There are new RF-CMOS performance trends in RF/mm-wave topologies to address the need for lower voltage operation. Some of these trends include: reducing the threshold voltage (VT), increasing transconductance (g_m) through positive feedback, using only one transistor between the supply voltage (V_DD) and ground, and adopting transformer-based power combining techniques.

Modifying standard topologies to have only one transistor between VDD and ground is another effective strategy for low-voltage RF/mm-wave circuits. The classical n-MOS cascode topology, commonly used in high-frequency amplifiers, cannot be used below a supply voltage of 1 V. Other more recently used viable alternatives include the neutralized common source (CS) topology, folded cascode topology, and reactive resonant coupling using either capacitive or transformer coupling.

Incorporating Cadence AWR software into your RF-CMOS design workflow can further enhance the implementation of these rf-cmos performance trends. With Cadence AWR, you can access advanced design and simulation tools that empower you to optimize your RF-CMOS circuits. Leverage the software's accurate device modeling capabilities to capture high-frequency behavior, including non-linear effects, parasitic components, and process variations, ensuring optimal circuit performance.

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