The ultimate goal for a high speed serial link is to lower the system Bit Error Rate (BER). While hardware results have the final say, simulation plays a key role in checking the system feasibility and predicting the performance margin. Systems applications often use SerDes components from multiple suppliers, requiring IBIS-AMI models for simulation interoperability. AMI simulation can be used to identify the marginal serial links in the overall system, among which are those that do not meet BER requirements. The BER of these links can be improved by the utilization of forward error correction (FEC) algorithms. This paper will present an end-to-end methodology in which AMI modeling techniques and existing serial link analysis is augmented with FEC to improve BER performance.