Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 51 3. Enter the following information in the table: Name value PCIE HSIO and Interface name PCIE HSIO Note: The Mapping table Name and Interface need to match the interface name in the Object and ObjectRule tables. Update the other information in the header as required. 4. Define information in the Data rows as follows: Header : Typ e Alias Design Data: * HSIO_ X J3_HSI:J3_H SO * HSIO_ RX J3_HSI * HSIO_T X J3_HSO * LANE {0-7} 5. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). 6. Open the starter Object table in the Lab-5_Virtex-7_to_PCIe_HSIO folder: object_grouping_PCI_HSIO.xlsx 7. Enter the following information in the table: Object name VIRTEX-7_TO_PCIE_HSIO and Interface name PCIE HSIO Update the other information in the header as required.