Allegro PCB Designer RAKs

Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 15 Column Header Descriptions Group or Kind Type of Group to create: DiffPair, Match Group, NetGroup, NetClass, ElectricalNetClass, PhysicalNetClass, SpacingNetClass, or SameNetSpacingNetClass Using NetClass will create both Physical and Spacing Net Classes. Leaving the field blank will create a Net Group of the objects. Name Name of the group that can be leveraged by Rule Specifications and Object Rule tables to drive rule assignment Group name will have the following prefix added to the name when imported into Constraint Manager: Physical CSet = "PCS_" , Spacing CSet = "SCS_" , Electrical CSet = "ECS_ " Net Class ="NC_" , Net Group = "NG_" , Match Group = "MG_" , Diff Pair = "DP_" Nets or Signals Net names using an Explicit Name, Number Range { - }, Regular Expression, or combination of Regular Expression and Number Range Type (optional) Type classification of objects to be referenced in Rule Specifications for rule assignment Can also be leveraged by other Rule Specification tables to generate Class-to-Class relationships with an associated Rule Set Rule (optional) Rule Specification and Rule Set reference for the selected objects Rule Specification Name:Rule Set Name Can also reference existing Constraint Set in Layout PhysicalCSet:, SpacingCSet:, etc. Multiple Rule Specifications or Constraint Sets from different domains can be listed, separated by a semicolon ";" Count (optional) Target membership count for a group of objects Compiler uses this value as a check to ensure that the correct number of members are found. Object Table Example Object MY_OBJECT Revision 1 Interface PCI Manufacturer Created by Cadence Header Group Name Nets Type Rule Count Data NetClass HS- PORT_DATA HD{0-31} HS-DATA SPC:HS_SPA CE 32 DiffPair HS-PORT_DP HSO[N,P](0) HS- DIFFP PHY:HS_DIFF P 2 End

• Cover
• Purpose
• Audience
• Terms
• Overview
• Benefits of ACC
• Functional Overview
• Table and Specification Format Overview
• Mapping Name Table
• Object Table
• Rule Specification Table (Rule Sets)
• Object Rule Table (Object Rules)
• Object Rule Table (Class-to-Class Rules)
• User Interface and Data Query
• Validation and Apply Constraints to Design
• Reporting
• ACC Lab Exercises
• License Requirements / Workshop Structure
• Lab 1-1: Rule Specifications Structure Review
• Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1)
• Lab 1-3: DSP (RefDes U2) To HS Connector (RefDes U4)
• Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2)
• Lab 1-5: VIRTEX-7 (RefDes U1) To PCIe HSIO (RefDes J3)
• Lab 1-6: Viper (RefDes U34) To PCIe CONN (RefDes J1)
• Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional
• Lab 1-8: Viper (RefDes U34) To SATA Connectors (RefDes J2,J7-9,J11,J12)
• Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1)
• Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35)
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