Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 80 3. Review the Object and Object Rule tables in Lab-10_Viper_ASIC_to_DDR3: object_grouping_DDR3_On-Board.xlsx objectrule_spec_DDR3_On-Board.xlsx objectrule_class_to_class_DDR3_On-Board.xlsx 4. Open the design-specific Mapping file in the main design folder and review the DDR3 SODIMM table (Name DDR3 SODIMM) at the bottom of the file: ACC_Workshop_mapping.xlsx 5. CSV files have already been created; so, move to the next step to run the compiler. Running the Compiler 6. Open Constraint Manager and select Tools > Constraint Compiler. 7. Select the acc_library and ACC_Workshop_mapping.csv folders. 8. Click the Load Selected Files button. 9. Double-click on Interface and Table Type under the Keys pane. 10. Select Interface under the Query Filter pane and change the Value under the Define Query Filter pane to On-Board DDR3.